Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 025477/0919 | |
| Pages: | 22 |
| | Recorded: | 12/08/2010 | | |
| Attorney Dkt #: | 60961-28001.00 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
3
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Patent #:
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Issue Dt:
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06/01/1999
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Application #:
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08580816
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Filing Dt:
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12/27/1995
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Title:
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METHOD TO FORM A BURIED IMPLANTED PLATE FOR DRAM TRENCH STORAGE CAPACITORS
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Patent #:
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Issue Dt:
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11/13/2001
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Application #:
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09282091
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Filing Dt:
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03/30/1999
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Title:
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EASY TO MANUFACTURE INTEGRATED SEMICONDUCTOR MEMORY CONFIGURATION WITH PLATINUM ELECTRODES
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09589439
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Filing Dt:
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06/07/2000
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Title:
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Integrated memory having memory cells disposed at crossover points of word lines and bit lines
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Assignee
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| ST. MARTIN STR. 53 |
| MUNICH, GERMANY 81541 |
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Correspondence name and address
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BARRY E. BRETSCHNEIDER
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C/O MORRISON & FOERSTER LLP
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1650 TYSONS BLVD STE 400
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MCLEAN, VA 22102
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