Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 025601/0237 | |
| Pages: | 4 |
| | Recorded: | 01/07/2011 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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06/13/1995
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Application #:
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08030458
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Filing Dt:
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04/01/1993
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Title:
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FLOATING GATE NONVOLATILE MEMORY WITH UNIFORMLY ERASED THRESHOLD VOLTAGE
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Patent #:
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Issue Dt:
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06/25/1996
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Application #:
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08442682
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Filing Dt:
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05/17/1995
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Title:
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FLOATING GATE NONVOLATILE MEMORY WITH UNIFORMLY ERASED THRESHOLD VOLTAGE
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08760823
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Filing Dt:
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12/05/1996
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Title:
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DRAM WITH HIDDEN REFRESH
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08919653
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Filing Dt:
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08/28/1997
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Title:
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SYSTEM FOR GENERATING BUFFER STATUS FLAGS BY COMPARING READ AND WRITE POINTERS AND DETERMINING DIRECTION OF PROGRESSION OF READ POINTER WITH RESPECT TO WRITE POINTER
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09385189
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Filing Dt:
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08/30/1999
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Title:
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ARCHITECTURE, CIRCUITRY AND METHOD FOR TESTING ONE OR MORE INTEGRATED CIRCUITS AND/OR RECEIVING TEST INFORMATION THEREFROM
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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10785826
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Filing Dt:
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02/23/2004
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Title:
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METHOD AND APPARATUS FOR BUILT-IN SELF-TEST (BIST) OF INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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11234028
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Filing Dt:
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09/23/2005
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Title:
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DUAL-VOLTAGE WORDLINE DRIVE CIRCUIT WITH TWO STAGE DISCHARGE
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Patent #:
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Issue Dt:
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07/01/2008
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Application #:
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11395416
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Filing Dt:
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03/31/2006
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Title:
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BANK AVAILABILITY INDICATIONS FOR MEMORY DEVICE AND METHOD THEREFOR
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Assignee
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| 1050 ENTERPRISE WAY |
| SUITE 700 |
| SUNNYVALE, CALIFORNIA 94089 |
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Correspondence name and address
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EDWARD J. GRUNDLER
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PARK, VAUGHAN, FLEMING & DOWLER LLP
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2820 FIFTH STREET
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DAVIS, CA 95618
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