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Total properties:
75
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Issue Dt:
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07/06/1999
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08606126
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02/23/1996
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Title:
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METHOD FOR FORMING A STORAGE CAPACITOR WITHIN AN INTEGRATED CIRCUIT
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Patent #:
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01/02/2001
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Application #:
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08630013
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Filing Dt:
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04/09/1996
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Title:
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METHOD FOR FABRICATING CROWN-SHAPED CAPACITOR STRUCTURES
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08649979
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Filing Dt:
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05/16/1996
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Title:
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METHOD TO FABRICATE CAPACITORS IN MEMORY CIRCUITS
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Patent #:
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02/09/1999
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Application #:
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08657217
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Filing Dt:
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06/03/1996
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Title:
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COAXIAL CAPACITOR FOR DRAM MEMORY CELL
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Patent #:
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Issue Dt:
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02/16/1999
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Application #:
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08851596
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Filing Dt:
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05/05/1997
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Title:
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TESTCHIP DESIGN FOR PROCESS ANALYSIS IN SUB-MICRON DRAM FABRICATION
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Patent #:
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Issue Dt:
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05/04/1999
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Application #:
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08861313
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Filing Dt:
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05/19/1997
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Title:
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OXYGEN ION IMPLANTATION PROCEDURE TO INCREASE THE SURFACE AREA OF AN STC STRUCTURE
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Patent #:
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Issue Dt:
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02/23/1999
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Application #:
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08880953
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Filing Dt:
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06/23/1997
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Title:
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METHOD TO IMPROVE YIELD FOR CAPACITORS FORMED USING ETCHBACK OF POLYSILICON HEMISHERICAL GRAINS
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Patent #:
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Issue Dt:
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05/18/1999
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Application #:
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08919393
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Filing Dt:
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08/28/1997
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Title:
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METHOD OF FORMING A DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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07/20/1999
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Application #:
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08956968
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Filing Dt:
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10/23/1997
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Title:
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METHOD FORMAKING DYNAMIC RANDOM ACCESS MEMORY CELLS USING A NOVEL STACKED CAPACITOR PROCESS
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Patent #:
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Issue Dt:
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07/13/1999
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Application #:
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08957674
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Filing Dt:
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10/24/1997
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Title:
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METHOD OF MAKING GREEK LETTER PSI SHAPED CAPACITOR FOR DRAW CIRCUITS
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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08957813
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Filing Dt:
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10/27/1997
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Title:
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METHOD FOR PLANARIZING DRAM CELLS
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Patent #:
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Issue Dt:
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07/20/1999
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Application #:
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08960137
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Filing Dt:
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10/29/1997
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Title:
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METHOD FOR FABRICATING A CROWN SHAPED CAPACITOR STRUCTURE
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Patent #:
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Issue Dt:
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02/16/1999
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Application #:
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08963457
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Filing Dt:
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11/03/1997
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Title:
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NEW FABRICATION METHOD FOR A DRAM CELL WITH BIPOLAR CHARGE AMPLIFICATION
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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08963458
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Filing Dt:
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11/03/1997
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Title:
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A CAPACITOR OVER BIT LINE STRUCTURE USING A STRAIGHT BIT LINE SHAPE
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Patent #:
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Issue Dt:
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08/24/1999
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Application #:
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08964808
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Filing Dt:
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11/05/1997
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Title:
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A METHOF OF FABRICATING A BURIED RESERVOIR CAPACITOR STRUCTURE FOR HIGH-DENSITY DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITS
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08974452
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Filing Dt:
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11/20/1997
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Title:
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METHOD FOR FABRICATING A DRAM CELL STRUCTURE ON AN SOI WAFER INCORPORATING A TWO DIMENSIONAL TRENCH CAPACITOR
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Patent #:
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Issue Dt:
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07/06/1999
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Application #:
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09018457
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Filing Dt:
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02/04/1998
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Title:
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DRAM CELL AND ARRAY TO STORE TWO-BIT DATA HAVING MERGED STACK CAPACITOR AND TRENCH CAPACITOR
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Patent #:
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Issue Dt:
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06/01/1999
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Application #:
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09018623
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Filing Dt:
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02/04/1998
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Title:
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DRAM CELL AND ARRAY TO STORE TWO-BIT DATA
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Patent #:
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Issue Dt:
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09/21/1999
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Application #:
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09024716
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Filing Dt:
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02/17/1998
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Title:
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METHOD FOR CROWN TYPE CAPACITOR IN DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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09031651
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Filing Dt:
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02/27/1998
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Title:
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METHOD FOR FABRICATING LOW RESISTANCE BIT LINE STRUCTURES, ALONG WITH BIT LINE STRUCTURES EXHIBITING LOW BIT LINE TO BIT LINE COUPLING CAPACITANCE
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Patent #:
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Issue Dt:
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03/09/1999
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Application #:
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09031652
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Filing Dt:
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02/27/1998
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Title:
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METHOD FOR FABRICATION OF A ONE GIGABIT CAPACITOR OVER BIT LINE DRAM CELL WITH AN AREA EQUAL TO EIGHT TIMES THE USED MINIMUM FEATURE
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Patent #:
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Issue Dt:
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01/12/1999
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Application #:
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09031683
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Filing Dt:
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02/27/1998
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Title:
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PROCESS FOR FABRICATING A HIGH PERFORMANCE LOGIC AND EMBEDDED DRAM DEVICES ON A SINGLE SEMICONDUCTOR CHIP
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Patent #:
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Issue Dt:
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06/29/1999
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Application #:
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09045978
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Filing Dt:
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03/17/1998
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Title:
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MULTI-LEVEL DRAM SENSING SCHEME
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Patent #:
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Issue Dt:
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04/27/1999
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Application #:
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09047543
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Filing Dt:
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03/25/1998
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Title:
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HEMISPHERICAL GRAINED POLYSILICON WITH IMPROVED ADHESION AND REDUCED CAPACITANCE DEPLETION
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Patent #:
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Issue Dt:
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01/18/2000
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Application #:
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09050212
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Filing Dt:
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03/30/1998
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Title:
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DRAM SENSING SCHEME AND ISOLATION CIRCUIT
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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09053536
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Filing Dt:
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04/01/1998
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Title:
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DESIGN AND A NOVEL PROCESS FOR FORMATION OF DRAM BIT LINE AND CAPACITOR NODE CONTACTS
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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09053853
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Filing Dt:
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04/02/1998
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Title:
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NEW BIT-LINE VOLTAGE LIMITING ISOLATION CIRCUIT
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Patent #:
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Issue Dt:
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02/09/1999
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Application #:
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09055443
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04/06/1998
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Title:
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DRAM SENSING SCHEME FOR ELIMINATING BIT-LINE COUPLING NOISE
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Patent #:
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Issue Dt:
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07/27/1999
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Application #:
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09066016
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Filing Dt:
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04/24/1998
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Title:
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METHOD FOR FABRICATING A STACKED, OR CROWN SHAPED CAPACITOR STRUCTURE
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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09066017
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Filing Dt:
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04/24/1998
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Title:
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METHOD FOR MAKING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS HAVING ZIGZAG-SHAPED STACKED CAPACITORS WITH INCREASED CAPACITANCE
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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09066018
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Filing Dt:
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04/24/1998
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Title:
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METHOD FOR MAKING DYNAMIC RANDOM ACCESS MEMORY CELLS HAVING BRUSH-SHAPED STACKED CAPACITORS PATTERNED FROM A HEMISPHERICAL GRAIN HARD MASK
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Patent #:
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Issue Dt:
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01/16/2001
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09075370
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Filing Dt:
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05/11/1998
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Title:
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METHOD OF FABRICATION OF CAPACITOR AND BIT-LINE AT SAME LEVEL FOR 8F2 DRAM CELL WITH MINIMUM BIT-LINE COUPLING NOISE
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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09085612
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Filing Dt:
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05/27/1998
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Title:
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WORD LINE RESISTANCE REDUCTION METHOD AND DESIGN FOR HIGH DENSITY MEMORY WITH RELAXED METAL PITCH
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Patent #:
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Issue Dt:
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06/27/2000
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Application #:
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09089549
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Filing Dt:
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06/03/1998
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Title:
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METHOD FOR FABRICATING INTERCONNECTION AND CAPACITORS OF A DRAM USING A SIMPLE GEOMETRY ACTIVE AREA, SELF-ALIGNED ETCHING, AND POLYSILICON PLUGS
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Patent #:
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Issue Dt:
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03/02/1999
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Application #:
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09094463
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Filing Dt:
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06/11/1998
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Title:
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RESOLUTION OF HEMISPHERICAL GRAINED SILICON PEELING AND ROW-DISTURB PROBLEMS FOR DYNAMIC RANDOM ACCESS MEMORY, STACKED CAPACITOR STRUCTURES
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Patent #:
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Issue Dt:
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04/20/1999
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Application #:
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09096046
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Filing Dt:
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06/11/1998
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Title:
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METHOD OF FORMING SEMICROWN-SHAPED STACKED CAPACITORS FOR DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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09096677
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Filing Dt:
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06/12/1998
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Title:
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METHOD FOR MANUFACTURING A REVERSE CROWN CAPACITOR FOR DRAM MEMORY CELL
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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09105104
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Filing Dt:
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06/25/1998
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Title:
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ONE STEP IN SITU DOPED AMORPHOUS SILICON LAYERS USED FOR SELECTIVE HEMISPHERICAL GRAIN SILICON FORMATION FOR CROWN SHAPED CAPACITOR APPLICATIONS
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Patent #:
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Issue Dt:
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04/04/2000
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Application #:
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09105185
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Filing Dt:
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06/26/1998
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Title:
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GROWTH ENHANCEMENT OF HEMISPHERICAL GRAIN SILICON ON A DOPED POLYSILICON STORAGE NODE CAPACITOR STRUCTURE, FOR DYNAMIC RANDOM ACCESS MEMORY APPLICATIONS
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Patent #:
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Issue Dt:
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06/15/1999
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09105384
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06/26/1998
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Title:
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METHOD OF SELECTIVE GROWTH OF A HEMISPHERICAL GRAIN SILICON LAYER ON THE OUTER SIDES OF A CROWN SHAPED DRAM CAPACITOR STRUCTURE
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Patent #:
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Issue Dt:
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11/21/2000
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09111685
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07/08/1998
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Title:
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METHOD OF FORMING A COB DRAM BY USING SELF-ALIGNED NODE AND BIT LINE CONTACT PLUG
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Issue Dt:
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01/04/2000
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09118036
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07/17/1998
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Title:
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METHOD FOR MAKING A PLANARIZED CAPACITOR-OVER-BIT-LINE STRUCTURE FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICES
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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09121693
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Filing Dt:
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07/24/1998
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Title:
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METHOD OF INCREASING THE SURFACE AREA OF A DRAM CAPACITOR STRUCTURE VIA THE USE OF HEMISPHERICAL GRAINED POLYSILICON
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Patent #:
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Issue Dt:
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04/13/1999
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Application #:
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09152311
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Filing Dt:
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09/14/1998
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Title:
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METHOD FOR FABRICATING CAPACITOR-UNDER-BIT LINE (CUB) DYNAMIC RANDOM ACCESS MEMORY (DRAM) USING TUNGSTEN LANDING PLUG CONTACTS
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Patent #:
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Issue Dt:
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04/20/1999
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Application #:
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09152313
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Filing Dt:
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09/14/1998
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Title:
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METHOD FOR FABRICATING DYNAMIC RANDOM ACCESS MEMORY (DRAM) BY SIMULTANEOUS FORMATION OF TUNGSTEIN BIT LINES AND TUNGSTEIN LANDING PLUG CONTACTS
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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09184342
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Filing Dt:
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11/02/1998
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Title:
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METHOD FOR SIMULTANEOUSLY FABRICATING CAPACITOR STRUCTURES, FOR GIGA-BIT DRAM CELLS, AND PERIPHERAL INTERCONNECT STRUCTURES, USING A DUAL DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09184343
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Filing Dt:
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11/02/1998
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Title:
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METHOD TO DECREASE CAPACITANCE DEPLETION, FOR A DRAM CAPACITOR, VIA SELECTIVE DEPOSITION OF A DOPED POLYSILICON LAYER ON A SELECTIVELY FORMED HEMISPHERICAL GRAIN SILICON LAYER
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Patent #:
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Issue Dt:
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09/21/1999
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Application #:
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09184345
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Filing Dt:
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11/02/1998
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Title:
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METHOD FOR SIMULTANEOUSLY FORMING CAPACITOR PLATE AND METAL CONTACT STRUCTURES FOR A HIGH DENSITY DRAM DEVICE
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Issue Dt:
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12/28/1999
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Application #:
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09196750
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Filing Dt:
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11/20/1998
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Title:
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DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS WITH MINIMUM ACTIVE CELLS WITH MINIMUM ACTIVE CELL AREAS USING SIDEWALL-SPACER BIT LINES
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Issue Dt:
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12/07/1999
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09199132
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Filing Dt:
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11/24/1998
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Title:
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FABRICATION METHOD AND STRUCTURE FOR A DRAM CELL WITH BIPOLAR CHARGE AMPLIFICATION
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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09208916
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Filing Dt:
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12/10/1998
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Title:
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TESTCHIP DESIGN FOR PROCESS ANALYSIS IN SUB-MICRON DRAM FABRICATION
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Patent #:
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Issue Dt:
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01/30/2001
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09216794
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12/21/1998
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Title:
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A METHOD TO FABRICATE A DRAM CELL WITH AN AREA EQUAL TO FIVE TIMES MINIMUM USED FEATURE, SQUARED
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04/25/2000
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09224718
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01/04/1999
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Title:
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METHOD FOR FORMING A MODIFIED CROWN SHAPED, DYNAMIC RANDOM ACCESS MEMORY, (DRAM), CAPACITOR STRUCTURE
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10/24/2000
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09248727
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02/11/1999
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Title:
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METHOD FOR FABRICATING CAPACITOR-OVER-BIT-LINE DYNAMIC RANDOM ACCESS MEMORY (DRAM) USING SELF-ALIGNED CONTACT ETCHING TECHNOLOGY
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12/14/1999
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09249258
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02/12/1999
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Title:
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METHOD OF MAKING LOCAL INTERCONNECTIONS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) CONTACT RESISTANCE AND REDUCED MASK SET
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01/25/2000
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09257836
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02/25/1999
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Title:
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DRAM CELL AND ARRAY TO STORE TWO-BIT DATA
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02/06/2001
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09257837
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02/25/1999
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Title:
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DRAM CELL AND ARRAY TO STORE TWO-BIT DATA HAVING MERGED STACK CAPACITOR AND TRENCH CAPACITOR
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09/05/2000
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09307209
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05/07/1999
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Title:
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METHOD FOR FORMING A HIGH SURFACE AREA CAPACITOR ELECTRODE FOR DRAM APPLICATIONS
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05/02/2000
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09313305
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05/17/1999
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Title:
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MEMORY WITH RELAXED METAL PITCH
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Patent #:
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Issue Dt:
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09/26/2000
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09318956
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Filing Dt:
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05/26/1999
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Title:
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METHOD FOR MAKING OPENINGS IN A PASSIVATION LAYER OVER POLYCIDE FUSES USING A SINGLE MASK WHILE FORMING RELIABLE TUNGSTEN VIA PLUGS ON DRAMS
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01/04/2000
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09318959
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05/26/1999
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Title:
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POST CHEMICAL MECHANICAL POLISHING, CLEAN PROCEDURE, USED FOR FABRICATION OF A CROWN SHAPED CAPACITOR STRUCTURE
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12/21/1999
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09320753
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05/27/1999
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Title:
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METHOD TO IMPROVE UNIFORMITY AND THE CRITICAL DIMENSIONS OF A DRAM GATE STRUCTURE
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09/05/2000
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09329110
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06/09/1999
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Title:
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METHOD OF FABRICATING DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09332430
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Filing Dt:
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06/14/1999
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Title:
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METHOD TO FABRICATE CAPACITOR STRUCTURES WITH VERY NARROW FEATURES USING SILYATED PHOTORESIST
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Patent #:
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Issue Dt:
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10/10/2000
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Application #:
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09360122
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Filing Dt:
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07/23/1999
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Title:
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METHOD FOR MAKING DYNAMIC RANDOM ACCESS MEMORY CELLS HAVING CACTUS-SHAPED STACKED CAPACITORS WITH INCREASED CAPACITANCE
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09373247
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Filing Dt:
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08/12/1999
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Title:
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NEW ETCH STOP LAYER USED FOR THE FABRICATION OF AN OVERLYING CROWN SHAPED STORAGE NODE STRUCTURE
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09379228
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Filing Dt:
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08/23/1999
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Title:
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METHOD FOR FABRICATING A DRAM CELL STRUCTURE ON AN SOI WAFER INCORPORATING A TWO DIMENSIONAL TRENCH CAPACITOR
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Patent #:
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Issue Dt:
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04/04/2000
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Application #:
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09389884
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Filing Dt:
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09/03/1999
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Title:
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ISOTROPIC ETCHING OF A HEMISPHERICAL GRAIN SILICON LAYER TO IMPROVE THE QUALITY OF AN OVERLYING DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09414099
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Filing Dt:
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10/07/1999
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Title:
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DRAM USING OXIDE PLUG IN BITLINE CONTACTS DURING FABRICATION
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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09422176
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Filing Dt:
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10/22/1999
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Title:
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A METHOD OF FORMING A RING SHAPED STORAGE NODE STRUCTURE FOR A DRAM CAPACITOR STRUCTURE
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09442498
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Filing Dt:
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11/18/1999
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Title:
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NEW DESIGN AND A NOVEL PROCESS FOR FORMATION OF DRAM BIT LINE AND CAPACITOR NODE CONTACTS
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09455357
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Filing Dt:
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12/06/1999
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Title:
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CAPACITOR OVER BIT LINE STRUCTURE USING A STRAIGHT BIT LINE SHAPE
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09510946
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Filing Dt:
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02/22/2000
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Title:
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Power down scheme for regulated sense amplifier power in dram
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09655026
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Filing Dt:
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09/05/2000
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Title:
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New scheme of capacitor and bit-line at same level and its fabrication method for 8F2 DRAM cell with minimum bit-line coupling noise
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09668131
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Filing Dt:
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09/22/2000
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Title:
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METHOD FOR MAKING DRAM USING AN OXIDE PLUG IN THE BITLINE CONTACTS DURING FABRICATION
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