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Reel/Frame:025808/0718   Pages: 5
Recorded: 02/15/2011
Attorney Dkt #:0120-11
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 30
1
Patent #:
6157570
Issue Dt:
12/05/2000
Application #:
09243973
Filing Dt:
02/04/1999
Title:
PROGRAM/ERASE ENDURANCE OF EEPROM MEMORY CELLS
2
Patent #:
6147904
Issue Dt:
11/14/2000
Application #:
09243974
Filing Dt:
02/04/1999
Title:
REDUNDANCY METHOD AND STRUCTURE FOR 2-BIT NON-VOLATILE MEMORY CELLS
3
Patent #:
6081456
Issue Dt:
06/27/2000
Application #:
09243976
Filing Dt:
02/04/1999
Title:
BIT LINE CONTROL CIRCUIT FOR A MEMORY ARRAY USING 2-BIT NON-VOLATILE MEMORY CELLS
4
Patent #:
6346442
Issue Dt:
02/12/2002
Application #:
09244316
Filing Dt:
02/04/1999
Title:
METHODS FOR FABRICATING A SEMICONDUCTOR CHIP HAVING CMOS DEVICES AND A FIELDLESS ARRAY
5
Patent #:
6181597
Issue Dt:
01/30/2001
Application #:
09244317
Filing Dt:
02/04/1999
Title:
EEPROM ARRAY USING 2-BIT NON-VOLATILE MEMORY CELLS WITH SERIAL READ OPERATIONS
6
Patent #:
6256231
Issue Dt:
07/03/2001
Application #:
09244529
Filing Dt:
02/04/1999
Title:
EEPROM ARRAY USING 2-BIT NON-VOLATILE MEMORY CELLS AND METHOD OF IMPLEMENTING SAME
7
Patent #:
6044022
Issue Dt:
03/28/2000
Application #:
09258059
Filing Dt:
02/26/1999
Title:
PROGRAMMABLE CONFIGURATION FOR EEPROMS INCLUDING 2-BIT NON-VOLATILE MEMORY CELL ARRAYS
8
Patent #:
6218695
Issue Dt:
04/17/2001
Application #:
09340979
Filing Dt:
06/28/1999
Title:
AREA EFFICIENT COLUMN SELECT CIRCUITRY FOR 2-BIT NON-VOLATILE MEMORY CELLS
9
Patent #:
6329691
Issue Dt:
12/11/2001
Application #:
09460277
Filing Dt:
12/13/1999
Title:
DEVICE FOR PROTECTION OF SENSITIVE GATE DIELECTRICS OF ADVANCED NON-VOLATILE MEMORY DEVICES FROM DAMAGE DUE TO PLASMA CHARGING
10
Patent #:
6297984
Issue Dt:
10/02/2001
Application #:
09474376
Filing Dt:
12/29/1999
Title:
STRUCTURE AND METHOD FOR PROTECTING INTEGRATED CIRCUITS DURING PLASMA PROCESSING
11
Patent #:
6458702
Issue Dt:
10/01/2002
Application #:
09522245
Filing Dt:
03/09/2000
Title:
METHODS FOR MAKING SEMICONDUCTOR CHIP HAVING BOTH SELF ALIGNED SILICIDE REGIONS AND NON-SELF ALIGNED SILICIDE REGIONS
12
Patent #:
6339540
Issue Dt:
01/15/2002
Application #:
09730611
Filing Dt:
12/05/2000
Title:
Content-addressable memory for virtual ground flash architectures
13
Patent #:
6351415
Issue Dt:
02/26/2002
Application #:
09821336
Filing Dt:
03/28/2001
Title:
Symmetrical non-volatile memory array architecture without neighbor effect
14
Patent #:
6421276
Issue Dt:
07/16/2002
Application #:
09927277
Filing Dt:
08/09/2001
Title:
METHOD AND APPARATUS FOR CONTROLLING ERASE OPERATIONS OF A NON-VOLATILE MEMORY SYSTEM
15
Patent #:
6532176
Issue Dt:
03/11/2003
Application #:
09963912
Filing Dt:
09/25/2001
Publication #:
US20030058690
Pub Dt:
03/27/2003
Title:
NON-VOLATILE MEMORY ARRAY WITH EQUALIZED BIT LINE POTENTIALS
16
Patent #:
6583066
Issue Dt:
06/24/2003
Application #:
09978447
Filing Dt:
10/15/2001
Publication #:
US20020016081
Pub Dt:
02/07/2002
Title:
METHODS FOR FABRICATING A SEMICONDUCTOR CHIP HAVING CMOS DEVICES AND FIELDLESS ARRAY
17
Patent #:
6686276
Issue Dt:
02/03/2004
Application #:
10226487
Filing Dt:
08/22/2002
Publication #:
US20030001220
Pub Dt:
01/02/2003
Title:
SEMICONDUCTOR CHIP HAVING BOTH POLYCIDE AND SALICIDE GATES AND METHODS FOR MAKING SAME
18
Patent #:
6765259
Issue Dt:
07/20/2004
Application #:
10233310
Filing Dt:
08/28/2002
Publication #:
US20040041199
Pub Dt:
03/04/2004
Title:
NON-VOLATILE MEMORY TRANSISTOR ARRAY IMPLEMENTING "H" SHAPED SOURCE/DRAIN REGIONS AND METHOD FOR FABRICATING SAME
19
Patent #:
6774704
Issue Dt:
08/10/2004
Application #:
10282484
Filing Dt:
10/28/2002
Publication #:
US20040080358
Pub Dt:
04/29/2004
Title:
CONTROL CIRCUIT FOR SELECTING THE GREATER OF TWO VOLTAGE SIGNALS
20
Patent #:
7016225
Issue Dt:
03/21/2006
Application #:
10305403
Filing Dt:
11/26/2002
Publication #:
US20040100822
Pub Dt:
05/27/2004
Title:
FOUR-BIT NON-VOLATILE MEMORY TRANSISTOR AND ARRAY
21
Patent #:
6836443
Issue Dt:
12/28/2004
Application #:
10341933
Filing Dt:
01/14/2003
Publication #:
US20040136256
Pub Dt:
07/15/2004
Title:
APPARATUS AND METHOD OF HIGH SPEED CURRENT SENSING FOR LOW VOLTAGE OPERATION
22
Patent #:
6959920
Issue Dt:
11/01/2005
Application #:
10659031
Filing Dt:
09/09/2003
Publication #:
US20050051838
Pub Dt:
03/10/2005
Title:
PROTECTION AGAINST IN-PROCESS CHARGING IN SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) MEMORIES
23
Patent #:
7060627
Issue Dt:
06/13/2006
Application #:
10659042
Filing Dt:
09/09/2003
Publication #:
US20050054161
Pub Dt:
03/10/2005
Title:
METHOD OF DECREASING CHARGING EFFECTS IN OXIDE-NITRIDE-OXIDE (ONO) MEMORY ARRAYS
24
Patent #:
6937523
Issue Dt:
08/30/2005
Application #:
10696728
Filing Dt:
10/27/2003
Publication #:
US20050088878
Pub Dt:
04/28/2005
Title:
NEIGHBOR EFFECT CANCELLATION IN MEMORY ARRAY ARCHITECTURE
25
Patent #:
7390718
Issue Dt:
06/24/2008
Application #:
10783466
Filing Dt:
02/20/2004
Publication #:
US20050186741
Pub Dt:
08/25/2005
Title:
SONOS EMBEDDED MEMORY WITH CVD DIELECTRIC
26
Patent #:
7439575
Issue Dt:
10/21/2008
Application #:
11065312
Filing Dt:
02/23/2005
Publication #:
US20050139903
Pub Dt:
06/30/2005
Title:
PROTECTION AGAINTS IN-PROCESS CHARGING IN SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) MEMORIES
27
Patent #:
7280405
Issue Dt:
10/09/2007
Application #:
11304168
Filing Dt:
12/13/2005
Publication #:
US20060126389
Pub Dt:
06/15/2006
Title:
INTEGRATOR-BASED CURRENT SENSING CIRCUIT FOR READING MEMORY CELLS
28
Patent #:
NONE
Issue Dt:
Application #:
11338418
Filing Dt:
01/23/2006
Publication #:
US20060255398
Pub Dt:
11/16/2006
Title:
Ultra-violet protected tamper resistant embedded EEPROM
29
Patent #:
7400538
Issue Dt:
07/15/2008
Application #:
11539156
Filing Dt:
10/05/2006
Publication #:
US20080084764
Pub Dt:
04/10/2008
Title:
NROM MEMORY DEVICE WITH ENHANCED ENDURANCE
30
Patent #:
7795087
Issue Dt:
09/14/2010
Application #:
12207542
Filing Dt:
09/10/2008
Publication #:
US20090011576
Pub Dt:
01/08/2009
Title:
ULTRA-VIOLET PROTECTED TAMPER RESISTANT EMBEDDED EEPROM
Assignor
1
TOWER SEMICONDUCTOR LTD.
Exec Dt:
12/28/2010
Assignee
1
ELPIDA MEMORY, INC.
2-1, YAESU 2-CHOME
CHUO-KU, TOKYO, JAPAN 104-0028
Correspondence name and address
STEVEN M. GRUSKIN
2100 PENNSYLVANIA AVENUE
WASHINGTON, DC 20037

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