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Reel/Frame:025849/0134   Pages: 2
Recorded: 02/23/2011
Attorney Dkt #:098211-0132
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
07/09/2013
Application #:
13032379
Filing Dt:
02/22/2011
Publication #:
Pub Dt:
08/25/2011
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, DESIGN METHOD, DESIGN APPARATUS, AND PROGRAM
Assignor
1
Exec Dt:
12/22/2010
Assignee
1
1753, SHIMONUMABE, NAKAHARA-KU
KAWASAKI-SHI, KANAGAWA, JAPAN
Correspondence name and address
FOLEY & LARDNER LLP
3000 K STREET NW
WASHINGTON, DC 20007

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