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Reel/Frame:026138/0613   Pages: 10
Recorded: 04/15/2011
Attorney Dkt #:60961-28001.00
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 122
Page 1 of 2
Pages: 1 2
1
Patent #:
7403439
Issue Dt:
07/22/2008
Application #:
11414364
Filing Dt:
05/01/2006
Publication #:
US20070253265
Pub Dt:
11/01/2007
Title:
BITLINE LEAKAGE LIMITING WITH IMPROVED VOLTAGE REGULATION
2
Patent #:
7880160
Issue Dt:
02/01/2011
Application #:
11438450
Filing Dt:
05/22/2006
Publication #:
US20070267619
Pub Dt:
11/22/2007
Title:
MEMORY USING TUNNELING FIELD EFFECT TRANSISTORS
3
Patent #:
7447107
Issue Dt:
11/04/2008
Application #:
11453946
Filing Dt:
06/15/2006
Publication #:
US20070297268
Pub Dt:
12/27/2007
Title:
RANDOM ACCESS MEMORY INCLUDING MULTIPLE STATE MACHINES
4
Patent #:
7457146
Issue Dt:
11/25/2008
Application #:
11455340
Filing Dt:
06/19/2006
Publication #:
US20070297221
Pub Dt:
12/27/2007
Title:
MEMORY CELL PROGRAMMED USING A TEMPERATURE CONTROLLED SET PULSE
5
Patent #:
7441070
Issue Dt:
10/21/2008
Application #:
11456063
Filing Dt:
07/06/2006
Publication #:
US20080010418
Pub Dt:
01/10/2008
Title:
METHOD FOR ACCESSING A NON-VOLATILE MEMORY VIA A VOLATILE MEMORY INTERFACE
6
Patent #:
7886122
Issue Dt:
02/08/2011
Application #:
11466312
Filing Dt:
08/22/2006
Publication #:
US20080052481
Pub Dt:
02/28/2008
Title:
METHOD AND CIRCUIT FOR TRANSMITTING A MEMORY CLOCK SIGNAL
7
Patent #:
7663909
Issue Dt:
02/16/2010
Application #:
11483873
Filing Dt:
07/10/2006
Publication #:
US20080006811
Pub Dt:
01/10/2008
Title:
INTEGRATED CIRCUIT HAVING A PHASE CHANGE MEMORY CELL INCLUDING A NARROW ACTIVE REGION WIDTH
8
Patent #:
7423445
Issue Dt:
09/09/2008
Application #:
11487472
Filing Dt:
07/17/2006
Publication #:
US20080012596
Pub Dt:
01/17/2008
Title:
METHOD AND SYSTEM FOR TRIMMING VOLTAGE OR CURRENT REFERENCES
9
Patent #:
7636250
Issue Dt:
12/22/2009
Application #:
11487875
Filing Dt:
07/17/2006
Publication #:
US20080013391
Pub Dt:
01/17/2008
Title:
RANDOM ACCESS MEMORY THAT SELECTIVELY PROVIDES DATA TO AMPLIFIERS
10
Patent #:
8084799
Issue Dt:
12/27/2011
Application #:
11488422
Filing Dt:
07/18/2006
Publication #:
US20080017894
Pub Dt:
01/24/2008
Title:
INTEGRATED CIRCUIT WITH MEMORY HAVING A STEP-LIKE PROGRAMMING CHARACTERISTIC
11
Patent #:
7688618
Issue Dt:
03/30/2010
Application #:
11488869
Filing Dt:
07/18/2006
Publication #:
US20080019170
Pub Dt:
01/24/2008
Title:
INTEGRATED CIRCUIT HAVING MEMORY HAVING A STEP-LIKE PROGRAMMING CHARACTERISTIC
12
Patent #:
7453081
Issue Dt:
11/18/2008
Application #:
11490213
Filing Dt:
07/20/2006
Publication #:
US20080017842
Pub Dt:
01/24/2008
Title:
PHASE CHANGE MEMORY CELL INCLUDING NANOCOMPOSITE INSULATOR
13
Patent #:
7405964
Issue Dt:
07/29/2008
Application #:
11494190
Filing Dt:
07/27/2006
Publication #:
US20080025079
Pub Dt:
01/31/2008
Title:
INTEGRATED CIRCUIT TO IDENTIFY READ DISTURB CONDITION IN MEMORY CELL
14
Patent #:
NONE
Issue Dt:
Application #:
11509367
Filing Dt:
08/24/2006
Publication #:
US20080050680
Pub Dt:
02/28/2008
Title:
Lithography systems and methods
15
Patent #:
7551476
Issue Dt:
06/23/2009
Application #:
11541973
Filing Dt:
10/02/2006
Publication #:
US20080080228
Pub Dt:
04/03/2008
Title:
RESISTIVE MEMORY HAVING SHUNTED MEMORY CELLS
16
Patent #:
7623401
Issue Dt:
11/24/2009
Application #:
11544159
Filing Dt:
10/06/2006
Publication #:
US20080084738
Pub Dt:
04/10/2008
Title:
SEMICONDUCTOR DEVICE INCLUDING MULTI-BIT MEMORY CELLS AND A TEMPERATURE BUDGET SENSOR
17
Patent #:
7405992
Issue Dt:
07/29/2008
Application #:
11552752
Filing Dt:
10/25/2006
Publication #:
US20080106967
Pub Dt:
05/08/2008
Title:
METHOD AND APPARATUS FOR COMMUNICATING COMMAND AND ADDRESS SIGNALS
18
Patent #:
7861138
Issue Dt:
12/28/2010
Application #:
11566774
Filing Dt:
12/05/2006
Publication #:
US20080133994
Pub Dt:
06/05/2008
Title:
ERROR CORRECTION IN MEMORY DEVICES
19
Patent #:
7385872
Issue Dt:
06/10/2008
Application #:
11581350
Filing Dt:
10/17/2006
Publication #:
US20080089164
Pub Dt:
04/17/2008
Title:
METHOD AND APPARATUS FOR INCREASING CLOCK FREQUENCY AND DATA RATE FOR SEMICONDUCTOR DEVICES
20
Patent #:
7577053
Issue Dt:
08/18/2009
Application #:
11598403
Filing Dt:
11/13/2006
Publication #:
US20080112250
Pub Dt:
05/15/2008
Title:
MEMORY INCLUDING DEEP POWER DOWN MODE
21
Patent #:
7619936
Issue Dt:
11/17/2009
Application #:
11600354
Filing Dt:
11/16/2006
Publication #:
US20080117697
Pub Dt:
05/22/2008
Title:
SYSTEM THAT PREVENTS REDUCTION IN DATA RETENTION
22
Patent #:
7679980
Issue Dt:
03/16/2010
Application #:
11602719
Filing Dt:
11/21/2006
Publication #:
US20080117704
Pub Dt:
05/22/2008
Title:
RESISTIVE MEMORY INCLUDING SELECTIVE REFRESH OPERATION
23
Patent #:
7539050
Issue Dt:
05/26/2009
Application #:
11603636
Filing Dt:
11/22/2006
Publication #:
US20080117663
Pub Dt:
05/22/2008
Title:
RESISTIVE MEMORY INCLUDING REFRESH OPERATION
24
Patent #:
7619917
Issue Dt:
11/17/2009
Application #:
11605079
Filing Dt:
11/28/2006
Publication #:
US20080123398
Pub Dt:
05/29/2008
Title:
MEMORY CELL WITH TRIGGER ELEMENT
25
Patent #:
7611972
Issue Dt:
11/03/2009
Application #:
11606812
Filing Dt:
11/29/2006
Publication #:
US20080121963
Pub Dt:
05/29/2008
Title:
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF
26
Patent #:
7639066
Issue Dt:
12/29/2009
Application #:
11611222
Filing Dt:
12/15/2006
Publication #:
US20080142854
Pub Dt:
06/19/2008
Title:
CIRCUIT AND METHOD FOR SUPPRESSING GATE INDUCED DRAIN LEAKAGE
27
Patent #:
7415387
Issue Dt:
08/19/2008
Application #:
11612541
Filing Dt:
12/19/2006
Publication #:
US20080147355
Pub Dt:
06/19/2008
Title:
DIE AND WAFER FAILURE CLASSIFICATION SYSTEM AND METHOD
28
Patent #:
7663955
Issue Dt:
02/16/2010
Application #:
11615101
Filing Dt:
12/22/2006
Publication #:
US20080151663
Pub Dt:
06/26/2008
Title:
DELAYED SENSE AMPLIFIER MULTIPLEXER ISOLATION
29
Patent #:
7443751
Issue Dt:
10/28/2008
Application #:
11615118
Filing Dt:
12/22/2006
Publication #:
US20080151647
Pub Dt:
06/26/2008
Title:
PROGRAMMABLE SENSE AMPLIFIER MULTIPLEXER CIRCUIT WITH DYNAMIC LATCHING MODE
30
Patent #:
7873857
Issue Dt:
01/18/2011
Application #:
11624465
Filing Dt:
01/18/2007
Publication #:
US20080177911
Pub Dt:
07/24/2008
Title:
MULTI-COMPONENT MODULE FLY-BY OUTPUT ALIGNMENT ARRANGEMENT AND METHOD
31
Patent #:
7692949
Issue Dt:
04/06/2010
Application #:
11633210
Filing Dt:
12/04/2006
Publication #:
US20080130351
Pub Dt:
06/05/2008
Title:
MULTI-BIT RESISTIVE MEMORY
32
Patent #:
7917825
Issue Dt:
03/29/2011
Application #:
11639161
Filing Dt:
12/15/2006
Publication #:
US20080148007
Pub Dt:
06/19/2008
Title:
METHOD AND APPARATUS FOR SELECTIVELY UTILIZING INFORMATION WITHIN A SEMICONDUCTOR DEVICE
33
Patent #:
8017930
Issue Dt:
09/13/2011
Application #:
11643438
Filing Dt:
12/21/2006
Publication #:
US20080149909
Pub Dt:
06/26/2008
Title:
PILLAR PHASE CHANGE MEMORY CELL
34
Patent #:
7564114
Issue Dt:
07/21/2009
Application #:
11644090
Filing Dt:
12/21/2006
Publication #:
US20080149980
Pub Dt:
06/26/2008
Title:
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF
35
Patent #:
7797511
Issue Dt:
09/14/2010
Application #:
11650120
Filing Dt:
01/05/2007
Publication #:
US20080168217
Pub Dt:
07/10/2008
Title:
MEMORY REFRESH SYSTEM AND METHOD
36
Patent #:
7515455
Issue Dt:
04/07/2009
Application #:
11650244
Filing Dt:
01/05/2007
Publication #:
US20070279962
Pub Dt:
12/06/2007
Title:
HIGH DENSITY MEMORY ARRAY FOR LOW POWER APPLICATION
37
Patent #:
7840876
Issue Dt:
11/23/2010
Application #:
11676774
Filing Dt:
02/20/2007
Publication #:
US20080201626
Pub Dt:
08/21/2008
Title:
POWER SAVINGS FOR MEMORY WITH ERROR CORRECTION MODE
38
Patent #:
7617354
Issue Dt:
11/10/2009
Application #:
11683629
Filing Dt:
03/08/2007
Publication #:
US20080219074
Pub Dt:
09/11/2008
Title:
ABBREVIATED BURST DATA TRANSFERS FOR SEMICONDUCTOR MEMORY
39
Patent #:
7765418
Issue Dt:
07/27/2010
Application #:
11686450
Filing Dt:
03/15/2007
Publication #:
US20080231242
Pub Dt:
09/25/2008
Title:
MULTI-MODE VOLTAGE SUPPLY CIRCUIT
40
Patent #:
7849349
Issue Dt:
12/07/2010
Application #:
11692245
Filing Dt:
03/28/2007
Publication #:
US20080238483
Pub Dt:
10/02/2008
Title:
REDUCED-DELAY CLOCKED LOGIC
41
Patent #:
7679984
Issue Dt:
03/16/2010
Application #:
11695676
Filing Dt:
04/03/2007
Publication #:
US20080247259
Pub Dt:
10/09/2008
Title:
CONFIGURABLE MEMORY DATA PATH
42
Patent #:
7539034
Issue Dt:
05/26/2009
Application #:
11701006
Filing Dt:
02/01/2007
Publication #:
US20080189480
Pub Dt:
08/07/2008
Title:
MEMORY CONFIGURED ON A COMMON SUBSTRATE
43
Patent #:
7800093
Issue Dt:
09/21/2010
Application #:
11701198
Filing Dt:
02/01/2007
Publication #:
US20080185571
Pub Dt:
08/07/2008
Title:
RESISTIVE MEMORY INCLUDING BURIED WORD LINES
44
Patent #:
7898847
Issue Dt:
03/01/2011
Application #:
11715749
Filing Dt:
03/08/2007
Publication #:
US20080219040
Pub Dt:
09/11/2008
Title:
METHOD TO PREVENT OVERRESET
45
Patent #:
8779495
Issue Dt:
07/15/2014
Application #:
11737531
Filing Dt:
04/19/2007
Publication #:
US20080258203
Pub Dt:
10/23/2008
Title:
STACKED SONOS MEMORY
46
Patent #:
7719886
Issue Dt:
05/18/2010
Application #:
11743987
Filing Dt:
05/03/2007
Publication #:
US20080273378
Pub Dt:
11/06/2008
Title:
MULTI-LEVEL RESISTIVE MEMORY CELL USING DIFFERENT CRYSTALLIZATION SPEEDS
47
Patent #:
7577023
Issue Dt:
08/18/2009
Application #:
11744487
Filing Dt:
05/04/2007
Publication #:
US20080273371
Pub Dt:
11/06/2008
Title:
MEMORY INCLUDING WRITE CIRCUIT FOR PROVIDING MULTIPLE RESET PULSES
48
Patent #:
7440347
Issue Dt:
10/21/2008
Application #:
11744790
Filing Dt:
05/04/2007
Publication #:
US20080273407
Pub Dt:
11/06/2008
Title:
CIRCUIT AND METHOD TO FIND WORDLINE-BITLINE SHORTS IN A DRAM
49
Patent #:
7956644
Issue Dt:
06/07/2011
Application #:
11746946
Filing Dt:
05/10/2007
Publication #:
US20080282001
Pub Dt:
11/13/2008
Title:
PEAK POWER REDUCTION USING FIXED BIT INVERSION
50
Patent #:
7671353
Issue Dt:
03/02/2010
Application #:
11757712
Filing Dt:
06/04/2007
Publication #:
US20080296553
Pub Dt:
12/04/2008
Title:
INTEGRATED CIRCUIT HAVING CONTACT INCLUDING MATERIAL BETWEEN SIDEWALLS
51
Patent #:
7977661
Issue Dt:
07/12/2011
Application #:
11759446
Filing Dt:
06/07/2007
Publication #:
US20080304310
Pub Dt:
12/11/2008
Title:
MEMORY HAVING SHARED STORAGE MATERIAL
52
Patent #:
7545019
Issue Dt:
06/09/2009
Application #:
11759528
Filing Dt:
06/07/2007
Publication #:
US20080304311
Pub Dt:
12/11/2008
Title:
INTEGRATED CIRCUIT INCLUDING LOGIC PORTION AND MEMORY PORTION
53
Patent #:
7975170
Issue Dt:
07/05/2011
Application #:
11763593
Filing Dt:
06/15/2007
Publication #:
US20080313494
Pub Dt:
12/18/2008
Title:
MEMORY REFRESH SYSTEM AND METHOD
54
Patent #:
7571901
Issue Dt:
08/11/2009
Application #:
11766201
Filing Dt:
06/21/2007
Publication #:
US20080316792
Pub Dt:
12/25/2008
Title:
CIRCUIT FOR PROGRAMMING A MEMORY ELEMENT
55
Patent #:
7745812
Issue Dt:
06/29/2010
Application #:
11766231
Filing Dt:
06/21/2007
Publication #:
US20080315172
Pub Dt:
12/25/2008
Title:
INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE
56
Patent #:
7838860
Issue Dt:
11/23/2010
Application #:
11766290
Filing Dt:
06/21/2007
Publication #:
US20080315359
Pub Dt:
12/25/2008
Title:
INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE
57
Patent #:
7796424
Issue Dt:
09/14/2010
Application #:
11766566
Filing Dt:
06/21/2007
Publication #:
US20080316802
Pub Dt:
12/25/2008
Title:
MEMORY DEVICE HAVING DRIFT COMPENSATED READ OPERATION AND ASSOCIATED METHOD
58
Patent #:
NONE
Issue Dt:
Application #:
11766819
Filing Dt:
06/22/2007
Publication #:
US20080316793
Pub Dt:
12/25/2008
Title:
INTEGRATED CIRCUIT INCLUDING CONTACT CONTACTING BOTTOM AND SIDEWALL OF ELECTRODE
59
Patent #:
7679074
Issue Dt:
03/16/2010
Application #:
11766822
Filing Dt:
06/22/2007
Publication #:
US20080315173
Pub Dt:
12/25/2008
Title:
INTEGRATED CIRCUIT HAVING MULTILAYER ELECTRODE
60
Patent #:
7545668
Issue Dt:
06/09/2009
Application #:
11766831
Filing Dt:
06/22/2007
Publication #:
US20080316794
Pub Dt:
12/25/2008
Title:
MUSHROOM PHASE CHANGE MEMORY HAVING A MULTILAYER ELECTRODE
61
Patent #:
7916524
Issue Dt:
03/29/2011
Application #:
11768540
Filing Dt:
06/26/2007
Publication #:
US20090003044
Pub Dt:
01/01/2009
Title:
PROGRAM METHOD WITH LOCALLY OPTIMIZED WRITE PARAMETERS
62
Patent #:
7812333
Issue Dt:
10/12/2010
Application #:
11770064
Filing Dt:
06/28/2007
Publication #:
US20090003032
Pub Dt:
01/01/2009
Title:
INTEGRATED CIRCUIT INCLUDING RESISTIVITY CHANGING MATERIAL HAVING A PLANARIZED SURFACE
63
Patent #:
7852657
Issue Dt:
12/14/2010
Application #:
11771747
Filing Dt:
06/29/2007
Publication #:
US20090003034
Pub Dt:
01/01/2009
Title:
MULTIPLE WRITE CONFIGURATIONS FOR A MEMORY CELL
64
Patent #:
7755338
Issue Dt:
07/13/2010
Application #:
11776688
Filing Dt:
07/12/2007
Publication #:
US20090015219
Pub Dt:
01/15/2009
Title:
VOLTAGE REGULATOR POLE SHIFTING METHOD AND APPARATUS
65
Patent #:
7646625
Issue Dt:
01/12/2010
Application #:
11778786
Filing Dt:
07/17/2007
Publication #:
US20090003035
Pub Dt:
01/01/2009
Title:
CONDITIONING OPERATIONS FOR MEMORY CELLS
66
Patent #:
7855542
Issue Dt:
12/21/2010
Application #:
11778799
Filing Dt:
07/17/2007
Publication #:
US20090021308
Pub Dt:
01/22/2009
Title:
VOLTAGE REGULATOR STARTUP METHOD AND APPARATUS
67
Patent #:
7719244
Issue Dt:
05/18/2010
Application #:
11778805
Filing Dt:
07/17/2007
Publication #:
US20090021229
Pub Dt:
01/22/2009
Title:
METHOD AND APPARATUS FOR ENABLING A VOLTAGE REGULATOR
68
Patent #:
7863593
Issue Dt:
01/04/2011
Application #:
11780849
Filing Dt:
07/20/2007
Publication #:
US20090020738
Pub Dt:
01/22/2009
Title:
INTEGRATED CIRCUIT INCLUDING FORCE-FILLED RESISTIVITY CHANGING MATERIAL
69
Patent #:
8898400
Issue Dt:
11/25/2014
Application #:
11781374
Filing Dt:
07/23/2007
Publication #:
US20090031077
Pub Dt:
01/29/2009
Title:
INTEGRATED CIRCUIT INCLUDING MULTIPLE MEMORY DEVICES
70
Patent #:
7525860
Issue Dt:
04/28/2009
Application #:
11790927
Filing Dt:
04/30/2007
Publication #:
US20080267258
Pub Dt:
10/30/2008
Title:
SYSTEM AND METHOD FOR MONITORING TEMPERATURE IN A MULTIPLE DIE PACKAGE
71
Patent #:
7802133
Issue Dt:
09/21/2010
Application #:
11819759
Filing Dt:
06/29/2007
Publication #:
US20090006887
Pub Dt:
01/01/2009
Title:
SYSTEM AND METHOD FOR ADDRESSING ERRORS IN A MULTIPLE-CHIP MEMORY DEVICE
72
Patent #:
7852677
Issue Dt:
12/14/2010
Application #:
11828254
Filing Dt:
07/25/2007
Publication #:
US20090027969
Pub Dt:
01/29/2009
Title:
METHOD OF USING HOT-CARRIER-INJECTION DEGRADATION AS A PROGRAMMABLE FUSE/SWITCH
73
Patent #:
7822910
Issue Dt:
10/26/2010
Application #:
11843550
Filing Dt:
08/22/2007
Publication #:
US20090052270
Pub Dt:
02/26/2009
Title:
METHOD OF FLEXIBLE MEMORY SEGMENT ASSIGNMENT USING A SINGLE CHIP SELECT
74
Patent #:
7710754
Issue Dt:
05/04/2010
Application #:
11843558
Filing Dt:
08/22/2007
Publication #:
US20090052267
Pub Dt:
02/26/2009
Title:
METHOD OF SIMPLE CHIP SELECT FOR MEMORY SUBSYSTEMS
75
Patent #:
7937631
Issue Dt:
05/03/2011
Application #:
11846482
Filing Dt:
08/28/2007
Publication #:
US20090063916
Pub Dt:
03/05/2009
Title:
METHOD FOR SELF-TEST AND SELF-REPAIR IN A MULTI-CHIP PACKAGE ENVIRONMENT
76
Patent #:
7548471
Issue Dt:
06/16/2009
Application #:
11859273
Filing Dt:
09/21/2007
Publication #:
US20090080582
Pub Dt:
03/26/2009
Title:
METHOD AND APPARATUS FOR ADJUSTING THE TIMING OF AN ELECTRONIC CIRCUIT
77
Patent #:
7688665
Issue Dt:
03/30/2010
Application #:
11860977
Filing Dt:
09/25/2007
Publication #:
US20090080279
Pub Dt:
03/26/2009
Title:
STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP
78
Patent #:
7882324
Issue Dt:
02/01/2011
Application #:
11928633
Filing Dt:
10/30/2007
Publication #:
US20090113158
Pub Dt:
04/30/2009
Title:
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Title:
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Title:
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Title:
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Assignor
1
QIMONDA NORTH AMERICA CORP
Exec Dt:
02/21/2011
Assignee
1
QIMONDA AG
GUSTAV-HEINEMANN-RING 212
MUNICH, GERMANY 81379
Correspondence name and address
BARRY E. BRETSCHNEIDER
C/O MORRISON & FOERSTER LLP
1650 TYSONS BLVD STE 400
MCLEAN, VA 22102

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