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Total properties:
18
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Patent #:
|
|
Issue Dt:
|
11/04/2003
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Application #:
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09805384
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Filing Dt:
|
03/13/2001
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Publication #:
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Pub Dt:
|
09/19/2002
| | | | |
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Title:
|
CACHE WAY PREDICTION BASED ON INSTRUCTION BASE REGISTER
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Patent #:
|
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Issue Dt:
|
01/13/2004
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Application #:
|
09887463
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Filing Dt:
|
06/22/2001
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Publication #:
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Pub Dt:
|
01/16/2003
| | | | |
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Title:
|
FAST AND ACCURATE CACHE WAY SELECTION
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|
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Patent #:
|
|
Issue Dt:
|
07/06/2004
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Application #:
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10136732
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Filing Dt:
|
05/01/2002
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Publication #:
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Pub Dt:
|
11/06/2003
| | | | |
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Title:
|
MEMORY REGION BASED DATA PRE-FETCHING
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Patent #:
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Issue Dt:
|
07/29/2008
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Application #:
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10218074
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Filing Dt:
|
08/12/2002
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Publication #:
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Pub Dt:
|
02/12/2004
| | | | |
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Title:
|
INSTRUCTION CACHE WAY PREDICTION FOR JUMP TARGETS
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Patent #:
|
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Issue Dt:
|
01/09/2007
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Application #:
|
10226158
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Filing Dt:
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08/23/2002
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Publication #:
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Pub Dt:
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02/26/2004
| | | | |
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Title:
|
PROCESSOR PREFETCH TO MATCH MEMORY BUS PROTOCOL CHARACTERISTICS
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|
|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
10242785
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Filing Dt:
|
09/13/2002
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|
Publication #:
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|
Pub Dt:
|
03/18/2004
| | | | |
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Title:
|
Translation lookaside buffer
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|
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Patent #:
|
|
Issue Dt:
|
12/30/2008
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Application #:
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10496537
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Filing Dt:
|
05/24/2004
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Publication #:
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Pub Dt:
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12/30/2004
| | | | |
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Title:
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REROUTING VLIW INSTRUCTIONS TO ACCOMMODATE EXECUTION UNITS DEACTIVATED UPON DETECTION BY DISPATCH UNITS OF DEDICATED INSTRUCTION ALERTING MULTIPLE SUCCESSIVE REMOVED NOPS
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|
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Patent #:
|
|
Issue Dt:
|
10/23/2007
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Application #:
|
10509562
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Filing Dt:
|
09/28/2004
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|
Publication #:
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Pub Dt:
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09/22/2005
| | | | |
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Title:
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COMMUNICATION PATH TO EACH PART OF DISTRIBUTED REGISTER FILE FROM FUNCTIONAL UNITS IN ADDITION TO PARTIAL COMMUNICATION NETWORK
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|
|
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Patent #:
|
|
Issue Dt:
|
01/10/2012
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Application #:
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10511512
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Filing Dt:
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10/14/2004
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|
Publication #:
|
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Pub Dt:
|
06/16/2005
| | | | |
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Title:
|
REGISTER SYSTEMS AND METHODS FOR A MULTI-ISSUE PROCESSOR
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|
|
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Patent #:
|
|
Issue Dt:
|
01/29/2013
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Application #:
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10530495
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Filing Dt:
|
04/06/2005
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Publication #:
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Pub Dt:
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01/05/2006
| | | | |
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Title:
|
DATA PROCESSING APPARATUS ADDRESS RANGE DEPENDENT PARALLELIZATION OF INSTRUCTIONS
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|
|
|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
10535591
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Filing Dt:
|
05/19/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
|
Title:
|
Using a cache miss pattern to address a stride prediction table
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
10546757
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Filing Dt:
|
08/24/2005
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|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
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Title:
|
REDUCING CACHE EFFECTS OF CERTAIN CODE PIECES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/30/2010
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Application #:
|
10552777
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Filing Dt:
|
10/12/2005
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|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
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Title:
|
PROCESSING OF A COMPILEABLE COMPUTER PROGRAM
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/02/2010
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Application #:
|
10570290
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Filing Dt:
|
02/28/2006
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2007
| | | | |
|
Title:
|
INTERGRATED CIRCUIT AND A METHOD OF CACHE REMAPPING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
10583052
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Filing Dt:
|
06/14/2006
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
|
Title:
|
MEMORY-EFFICIENT INSTRUCTION PROCESSING SCHEME
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|
|
|
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Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
10585801
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Filing Dt:
|
07/12/2006
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
|
Title:
|
METHOD AND RELATED DEVICE FOR USE IN DECODING EXECUTABLE CODE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11099231
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Filing Dt:
|
04/04/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2005
| | | | |
|
Title:
|
DYNAMICALLY CONTROLLING EXECUTION OF OPERATIONS WITHIN A MULTI-OPERATION INSTRUCTION
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11719399
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Filing Dt:
|
05/11/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
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Title:
|
CACHE WITH PREFETCH
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|
