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Total properties:
12
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Patent #:
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Issue Dt:
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08/02/2011
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Application #:
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11153747
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Filing Dt:
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06/15/2005
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Publication #:
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Pub Dt:
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12/21/2006
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Title:
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GRAIN BOUNDARY BLOCKING FOR STRESS MIGRATION AND ELECTROMIGRATION IMPROVEMENT IN CU INTERCONNECTS
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Patent #:
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Issue Dt:
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09/13/2011
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Application #:
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11399016
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Filing Dt:
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04/05/2006
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Publication #:
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Pub Dt:
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10/11/2007
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Title:
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METHOD TO CONTROL SOURCE/DRAIN STRESSOR PROFILES FOR STRESS ENGINEERING
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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11865563
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Filing Dt:
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10/01/2007
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Publication #:
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Pub Dt:
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04/02/2009
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Title:
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POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT
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Patent #:
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Issue Dt:
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08/16/2011
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Application #:
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12062534
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Filing Dt:
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04/04/2008
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Publication #:
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Pub Dt:
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10/09/2008
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Title:
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PLANARIZED PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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09/06/2011
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Application #:
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12062535
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Filing Dt:
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04/04/2008
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Publication #:
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Pub Dt:
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10/08/2009
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Title:
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AN INTEGRATED CIRCUIT INCLUDING A STRESSED DIELECTRIC LAYER WITH STABLE STRESS
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Patent #:
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Issue Dt:
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08/16/2011
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Application #:
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12241073
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Filing Dt:
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09/30/2008
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Publication #:
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Pub Dt:
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01/29/2009
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Title:
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METHOD TO REMOVE SPACER AFTER SALICIDATION TO ENHANCE CONTACT ETCH STOP LINER STRESS ON MOS
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Patent #:
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Issue Dt:
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08/16/2011
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Application #:
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12361521
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Filing Dt:
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01/28/2009
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Publication #:
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Pub Dt:
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07/29/2010
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Title:
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MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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12616150
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Filing Dt:
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11/11/2009
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Publication #:
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Pub Dt:
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05/13/2010
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Title:
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MOS VARACTORS WITH LARGE TUNING RANGE
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Patent #:
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Issue Dt:
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08/23/2011
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Application #:
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12693405
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Filing Dt:
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01/25/2010
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Publication #:
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Pub Dt:
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05/13/2010
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Title:
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METHOD OF FABRICATION AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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08/30/2011
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Application #:
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12790975
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Filing Dt:
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05/31/2010
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Publication #:
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Pub Dt:
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09/16/2010
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Title:
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SELECTIVE STI STRESS RELAXATION THROUGH ION IMPLANTATION
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Patent #:
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Issue Dt:
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05/31/2011
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Application #:
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12819228
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Filing Dt:
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06/21/2010
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Publication #:
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Pub Dt:
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10/14/2010
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Title:
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LATERAL JUNCTION VARACTOR WITH LARGE TUNING RANGE
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Patent #:
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Issue Dt:
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06/14/2011
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Application #:
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12825325
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Filing Dt:
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06/28/2010
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Publication #:
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Pub Dt:
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10/21/2010
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Title:
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METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS
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