Patent Assignment Details
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| Reel/Frame: | 026453/0516 | |
| Pages: | 5 |
| | Recorded: | 06/16/2011 | | |
| Attorney Dkt #: | XA-11924/T3381-18465US01 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13159116
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Filing Dt:
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06/13/2011
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Publication #:
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Pub Dt:
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12/15/2011
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Title:
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METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE BASED ON TIMING VERIFICATION OF POWER-SUPPLY PATH
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Assignees
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| 1753, SHIMONUMABE, NAKAHARA-KU, |
| KAWASAKI-SHI, KANAGAWA, JAPAN 211-8668 |
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| 1-1, SHIBAURA 1-CHOME |
| MINATO-KU, TOKYO, JAPAN |
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| 1-7-1, KONAN |
| MINATO-KU, TOKYO, JAPAN |
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Correspondence name and address
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MITCHELL W. SHAPIRO
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1751 PINNACLE DRIVE, SUITE 500
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MCLEAN, VA 22102-3833
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