Total properties:
45
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Patent #:
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Issue Dt:
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07/11/1995
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Application #:
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08308310
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Filing Dt:
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09/19/1994
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Title:
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METHOD FOR FABRICATING SELF-ALIGNED POLYSILICON CONTACTS ON FET SOURCE/DRAIN AREAS
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Patent #:
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Issue Dt:
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08/01/1995
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Application #:
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08342873
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Filing Dt:
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11/21/1994
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Title:
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SILICON-ON-INSULATOR TECHNIQUE WITH BURIED GAP
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Patent #:
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Issue Dt:
|
04/20/1999
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Application #:
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08541600
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Filing Dt:
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10/10/1995
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Title:
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METHOD OF AND MEANS FOR ACCESSING AN ADDRESS BY RESPECTIVELY SUBSTRACTING BASE ADDRESSES OF MEMORY INTEGRATED CIRCUITS FROM AN ACCESS ADDRESS
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Patent #:
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Issue Dt:
|
06/16/1998
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Application #:
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08554490
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Filing Dt:
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11/07/1995
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Title:
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COMPUTER KEYBOARD POWER SAVING METHOD
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Patent #:
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Issue Dt:
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11/03/1998
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Application #:
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08630024
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Filing Dt:
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04/09/1996
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Title:
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ELECTROSTIC DISCHARGE PROTECTION DEVICE COMPRISING A PLURALITY OF TRENCHES
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Patent #:
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Issue Dt:
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03/23/1999
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Application #:
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08735007
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Filing Dt:
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10/22/1996
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Title:
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SRAM HAVING IMPROVED SOFT-ERROR IMMUNITY
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Patent #:
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Issue Dt:
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10/12/1999
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Application #:
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08890363
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Filing Dt:
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07/09/1997
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Title:
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METHOD OF MANUFACTURING MOS COMPONENTS HAVING LIGHTLY DOPED DRAIN STRUCTURES
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Patent #:
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Issue Dt:
|
03/02/1999
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Application #:
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08965581
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Filing Dt:
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11/06/1997
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Title:
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DYNAMIC INPUT REFERENCE VOLTAGE ADJUSTER
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Patent #:
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Issue Dt:
|
09/28/1999
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Application #:
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08975490
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Filing Dt:
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11/21/1997
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Title:
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FLASH EEPROM DEVICE
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Patent #:
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Issue Dt:
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05/25/1999
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Application #:
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08998312
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Filing Dt:
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12/24/1997
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Title:
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SPLIT-GATE FLASH MEMORY CELL STRUCTURE
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Patent #:
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Issue Dt:
|
02/16/1999
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Application #:
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08998331
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Filing Dt:
|
12/24/1997
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Title:
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METHOD OF MANUFACTURING A SPLIT-GATE FLASH MEMORY CELL
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Patent #:
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Issue Dt:
|
05/18/1999
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Application #:
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09002930
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Filing Dt:
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01/05/1998
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Title:
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METHOD OF FABRICATING A CMOS TRANSISTOR
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|
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Patent #:
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Issue Dt:
|
05/02/2000
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Application #:
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09057905
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Filing Dt:
|
04/09/1998
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Title:
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METHOD OF FORMING SHALLOW TRENCH ISOATION
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Patent #:
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|
Issue Dt:
|
02/15/2000
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Application #:
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09073576
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Filing Dt:
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05/06/1998
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Title:
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METHOD OF FABRICATING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED SILICIDE
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|
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Patent #:
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|
Issue Dt:
|
12/14/1999
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Application #:
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09164856
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Filing Dt:
|
10/01/1998
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Title:
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METHOD OF FORMING A DUAL DAMASCENE WITH DUMMY METAL LINES
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|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
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Application #:
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09186748
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Filing Dt:
|
11/05/1998
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Title:
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FLASH MEMORY STRUCTURE AND METHOD OF MANUFACTURE
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|
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Patent #:
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|
Issue Dt:
|
11/28/2000
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Application #:
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09191247
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Filing Dt:
|
11/12/1998
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Title:
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METHOD OF FABRICATING A BURIED CONTACT
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|
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Patent #:
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|
Issue Dt:
|
09/18/2001
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Application #:
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09191762
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Filing Dt:
|
11/13/1998
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Title:
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METHOD OF AUTOMATICALLY FORMING A RIM PHASE SHIFTING MASK
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|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
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Application #:
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09195744
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Filing Dt:
|
11/18/1998
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Title:
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METHOD OF FORMING MIXED MODE DEVICES
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|
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Patent #:
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|
Issue Dt:
|
07/24/2001
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Application #:
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09203035
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Filing Dt:
|
12/01/1998
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Title:
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DUAL DAMASCENE STRUCTURE FOR THE WIRING-LINE STRUCTURES OF MULTI-LEVEL INTERCONNECTS IN INTEGRATED CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
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Application #:
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09203711
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Filing Dt:
|
12/02/1998
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Title:
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METHOD OF FABRICATING HIGH POWER BIPOLAR JUNCTION TRANSISTOR
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|
|
Patent #:
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|
Issue Dt:
|
11/28/2000
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Application #:
|
09205912
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Filing Dt:
|
12/04/1998
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Title:
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METHOD OF FABRICATING A DUAL DAMASCENE STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
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Application #:
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09227761
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Filing Dt:
|
01/08/1999
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Title:
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METHOD OF FABRICATING DUAL GATE
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|
|
Patent #:
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|
Issue Dt:
|
01/02/2001
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Application #:
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09237787
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Filing Dt:
|
01/26/1999
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Title:
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METHOD FABRICATING METAL INTERCONNECTED STRUCTURE
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|
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Patent #:
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|
Issue Dt:
|
02/20/2001
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Application #:
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09243740
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Filing Dt:
|
02/03/1999
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Title:
|
METHOD FOR FABRICATING METAL OXIDE SEMICONDUCTOR
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|
|
Patent #:
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|
Issue Dt:
|
07/31/2001
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Application #:
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09248159
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Filing Dt:
|
02/09/1999
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Title:
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METHOD FOR FORMING DUAL DAMASCENE STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
10/26/1999
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Application #:
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09270026
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Filing Dt:
|
03/16/1999
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Title:
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METHOD FOR MANUFACTURING MOS TRANSISTOR
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|
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Patent #:
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|
Issue Dt:
|
05/09/2000
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Application #:
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09286139
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Filing Dt:
|
04/05/1999
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Title:
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METHOD OF MANUFACTURING FLASH MEMORY
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|
|
Patent #:
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|
Issue Dt:
|
11/09/1999
|
Application #:
|
09299255
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Filing Dt:
|
04/26/1999
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Title:
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METHOD FOR MANUFACTURING CMOS
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|
|
Patent #:
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|
Issue Dt:
|
02/27/2001
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Application #:
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09340929
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Filing Dt:
|
06/28/1999
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Title:
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FABRICATION METHOD FOR GATE SPACER
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|
|
Patent #:
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|
Issue Dt:
|
07/24/2001
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Application #:
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09431954
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Filing Dt:
|
11/01/1999
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Title:
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METHOD OF A METAL OXIDE SEMICONDUCTOR ON A SEMCONDUCTOR WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
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Application #:
|
09531905
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Filing Dt:
|
03/20/2000
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Title:
|
Electrostatic discharge protection circuit
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|
|
Patent #:
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|
Issue Dt:
|
03/05/2002
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Application #:
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09557513
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Filing Dt:
|
04/25/2000
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Title:
|
High voltage electrostatic discharge protection circuit
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|
|
Patent #:
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|
Issue Dt:
|
09/25/2001
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Application #:
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09558220
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Filing Dt:
|
04/26/2000
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Title:
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Method of fabricating a mos transistor
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|
|
Patent #:
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|
Issue Dt:
|
04/16/2002
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Application #:
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09584698
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Filing Dt:
|
06/01/2000
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Title:
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PHOTO MASK WITH AN ESD PROTECTIVE FUNCTION
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|
|
Patent #:
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|
Issue Dt:
|
08/20/2002
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Application #:
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09590721
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Filing Dt:
|
06/08/2000
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Title:
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METHOD FOR MANUFACTURING A FLASH MEMORY WITH SPLIT GATE CELLS
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|
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Patent #:
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|
Issue Dt:
|
09/10/2002
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Application #:
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09597744
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Filing Dt:
|
06/19/2000
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Title:
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CASSETTE HOLDER FOR CLEANING EQUIPMENT
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|
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Patent #:
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|
Issue Dt:
|
06/04/2002
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Application #:
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09764329
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Filing Dt:
|
01/19/2001
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Title:
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METHOD OF PREVENTING DISHING PHENOMENON ATOP A DUAL DAMASCENE STRUCTURE
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|
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Patent #:
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|
Issue Dt:
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08/20/2002
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Application #:
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09764330
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Filing Dt:
|
01/19/2001
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Publication #:
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|
Pub Dt:
|
07/25/2002
| | | | |
Title:
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METHOD FOR FABRICATING A MOS TRANSISTOR OF AN EMBEDDED MEMORY
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|
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Patent #:
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|
Issue Dt:
|
08/20/2002
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Application #:
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09779540
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Filing Dt:
|
02/09/2001
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Publication #:
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|
Pub Dt:
|
08/15/2002
| | | | |
Title:
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METHOD OF FABRICATING A TRENCHED FLASH MEMORY CELL
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|
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Patent #:
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|
Issue Dt:
|
06/25/2002
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Application #:
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09845438
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Filing Dt:
|
04/30/2001
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Title:
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METHOD OF FORMING POLYSILICON THIN FILM TRANSISTOR STRUCTURE
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|
|
Patent #:
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|
Issue Dt:
|
05/21/2002
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Application #:
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09854872
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Filing Dt:
|
05/14/2001
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Title:
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METHOD FOR FORMING A DUAL DAMASCENE STRUCTURE HAVING CAPACITORS
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|
|
Patent #:
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|
Issue Dt:
|
10/08/2002
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Application #:
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09885049
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Filing Dt:
|
06/21/2001
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Title:
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METHOD FOR FABRICATION OF A CONTACT PLUG IN AN EMBEDDED MEMORY
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|
|
Patent #:
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|
Issue Dt:
|
11/26/2002
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Application #:
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09994322
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Filing Dt:
|
11/26/2001
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Publication #:
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|
Pub Dt:
|
10/24/2002
| | | | |
Title:
|
POLYSILICON THIN FILM TRANSISTOR STRUCTURE
|
|
|
Patent #:
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|
Issue Dt:
|
11/19/2002
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Application #:
|
10108611
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Filing Dt:
|
03/27/2002
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Publication #:
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|
Pub Dt:
|
11/14/2002
| | | | |
Title:
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DUAL DAMASCENE STRUCTURE HAVING CAPACITORS
|
|