Patent Assignment Details
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| Reel/Frame: | 026667/0850 | |
| Pages: | 2 |
| | Recorded: | 07/28/2011 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12843500
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Filing Dt:
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07/26/2010
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Publication #:
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Pub Dt:
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11/11/2010
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Title:
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EXTERNAL I/O SIGNAL AND DRAM REFRESH SIGNAL SYNCHRONIZATION METHOD AND ITS CIRCUIT
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Assignee
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| 1006 OAZA KADOMA, KADOMA-SHI |
| OSAKA, JAPAN 571-8501 |
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Correspondence name and address
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YOSHINOBU IDOGAWA
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1130 CONNECTICUT AVE., N.W., SUITE 1100
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PANASONIC PATENT CENTER
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WASHINGTON, DC 20036
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04/29/2024 03:47 PM
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