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Total properties:
11
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11844074
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Filing Dt:
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08/23/2007
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Publication #:
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Pub Dt:
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02/26/2009
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Title:
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METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE HAVING HETEROGENEOUS CRYSTALLINE ORIENTATIONS
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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11862865
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Filing Dt:
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09/27/2007
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Publication #:
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Pub Dt:
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04/02/2009
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Title:
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METHOD OF FABRICATING A NITROGENATED SILICON OXIDE LAYER AND MOS DEVICE HAVING SAME
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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11959034
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Filing Dt:
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12/18/2007
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Publication #:
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Pub Dt:
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06/18/2009
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Title:
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THIN FILM ETCHING METHOD AND SEMICONDUCTOR DEVICE FABRICATION USING SAME
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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11965415
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Filing Dt:
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12/27/2007
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Publication #:
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Pub Dt:
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07/02/2009
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Title:
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PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING EMBEDDED EPITAXIAL REGIONS
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Patent #:
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Issue Dt:
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09/14/2010
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Application #:
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12030598
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Filing Dt:
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02/13/2008
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Publication #:
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Pub Dt:
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08/13/2009
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Title:
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METHOD FOR FABRICATING DEVICE STRUCTURES HAVING A VARIATION IN ELECTRICAL CONDUCTIVITY
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Patent #:
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Issue Dt:
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03/27/2012
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Application #:
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12046151
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Filing Dt:
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03/11/2008
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Publication #:
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Pub Dt:
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09/17/2009
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Title:
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POLISHING METHOD WITH INERT GAS INJECTION
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Patent #:
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Issue Dt:
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10/19/2010
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Application #:
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12057072
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Filing Dt:
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03/27/2008
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Publication #:
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Pub Dt:
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10/01/2009
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Title:
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METHODS FOR NORMALIZING STRAIN IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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04/24/2012
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Application #:
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12134860
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Filing Dt:
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06/06/2008
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Publication #:
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Pub Dt:
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12/10/2009
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Title:
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HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER
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Patent #:
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Issue Dt:
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06/07/2011
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Application #:
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12172756
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Filing Dt:
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07/14/2008
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Publication #:
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Pub Dt:
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01/14/2010
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Title:
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SEMICONDUCTOR FABRICATION PROCESS INCLUDING AN SIGE REWORK METHOD
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Patent #:
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Issue Dt:
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02/15/2011
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Application #:
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12271262
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Filing Dt:
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11/14/2008
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Publication #:
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Pub Dt:
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05/20/2010
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Title:
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METHOD FOR FORMING A SHALLOW JUNCTION REGION USING DEFECT ENGINEERING AND LASER ANNEALING
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Patent #:
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Issue Dt:
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05/06/2014
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Application #:
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13190805
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Filing Dt:
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07/26/2011
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Publication #:
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Pub Dt:
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11/17/2011
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Title:
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METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL CHANNEL AND TRANSISTOR HAVING SAME
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