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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:027133/0896   Pages: 6
Recorded: 10/26/2011
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 21
1
Patent #:
6954826
Issue Dt:
10/11/2005
Application #:
10442718
Filing Dt:
05/21/2003
Publication #:
US20040236911
Pub Dt:
11/25/2004
Title:
READ ACCESS AND STORAGE CIRCUITRY READ ALLOCATION APPLICABLE TO A CACHE
2
Patent #:
7237149
Issue Dt:
06/26/2007
Application #:
11065898
Filing Dt:
02/25/2005
Publication #:
US20060195721
Pub Dt:
08/31/2006
Title:
METHOD AND APPARATUS FOR QUALIFYING DEBUG OPERATION USING SOURCE INFORMATION
3
Patent #:
7433803
Issue Dt:
10/07/2008
Application #:
11116672
Filing Dt:
04/27/2005
Publication #:
US20060248410
Pub Dt:
11/02/2006
Title:
PERFORMANCE MONITOR WITH PRECISE START-STOP CONTROL
4
Patent #:
7447944
Issue Dt:
11/04/2008
Application #:
11118827
Filing Dt:
04/29/2005
Publication #:
US20060245248
Pub Dt:
11/02/2006
Title:
PREDICTIVE METHODS AND APPARATUS FOR NON-VOLATILE MEMORY
5
Patent #:
7185148
Issue Dt:
02/27/2007
Application #:
11197830
Filing Dt:
08/05/2005
Publication #:
US20050273562
Pub Dt:
12/08/2005
Title:
READ ACCESS AND STORAGE CIRCUITRY READ ALLOCATION APPLICABLE TO A CACHE
6
Patent #:
7292473
Issue Dt:
11/06/2007
Application #:
11220733
Filing Dt:
09/07/2005
Publication #:
US20070053222
Pub Dt:
03/08/2007
Title:
METHOD AND APPARATUS FOR PROGRAMMING/ERASING A NON-VOLATILE MEMORY
7
Patent #:
7376807
Issue Dt:
05/20/2008
Application #:
11360926
Filing Dt:
02/23/2006
Publication #:
US20070198804
Pub Dt:
08/23/2007
Title:
DATA PROCESSING SYSTEM HAVING ADDRESS TRANSLATION BYPASS AND METHOD THEREFOR
8
Patent #:
7809936
Issue Dt:
10/05/2010
Application #:
11461811
Filing Dt:
08/02/2006
Publication #:
US20080051075
Pub Dt:
02/28/2008
Title:
METHOD AND APPARATUS FOR RECONFIGURING A REMOTE DEVICE
9
Patent #:
7400545
Issue Dt:
07/15/2008
Application #:
11469074
Filing Dt:
08/31/2006
Publication #:
US20080055966
Pub Dt:
03/06/2008
Title:
STORAGE CIRCUIT WITH EFFICIENT SLEEP MODE AND METHOD
10
Patent #:
7453756
Issue Dt:
11/18/2008
Application #:
11469084
Filing Dt:
08/31/2006
Publication #:
US20080056049
Pub Dt:
03/06/2008
Title:
METHOD FOR POWERING AN ELECTRONIC DEVICE AND CIRCUIT
11
Patent #:
7555605
Issue Dt:
06/30/2009
Application #:
11536085
Filing Dt:
09/28/2006
Publication #:
US20080082720
Pub Dt:
04/03/2008
Title:
DATA PROCESSING SYSTEM HAVING CACHE MEMORY DEBUGGING SUPPORT AND METHOD THEREFOR
12
Patent #:
7853834
Issue Dt:
12/14/2010
Application #:
11668780
Filing Dt:
01/30/2007
Publication #:
US20080184055
Pub Dt:
07/31/2008
Title:
INSTRUCTION-BASED TIMER CONTROL DURING DEBUG
13
Patent #:
7831862
Issue Dt:
11/09/2010
Application #:
11668787
Filing Dt:
01/30/2007
Publication #:
US20080184056
Pub Dt:
07/31/2008
Title:
SELECTIVE TIMER CONTROL DURING SINGLE-STEP INSTRUCTION EXECUTION
14
Patent #:
7779284
Issue Dt:
08/17/2010
Application #:
11678440
Filing Dt:
02/23/2007
Publication #:
US20080209233
Pub Dt:
08/28/2008
Title:
TECHNIQUES FOR OPERATING A PROCESSOR SUBSYSTEM TO SERVICE MASKED INTERRUPTS DURING A POWER-DOWN SEQUENCE
15
Patent #:
7649782
Issue Dt:
01/19/2010
Application #:
11831168
Filing Dt:
07/31/2007
Publication #:
US20090034339
Pub Dt:
02/05/2009
Title:
NON-VOLATILE MEMORY HAVING A DYNAMICALLY ADJUSTABLE SOFT PROGRAM VERIFY VOLTAGE LEVEL AND METHOD THEREFOR
16
Patent #:
7689815
Issue Dt:
03/30/2010
Application #:
11871847
Filing Dt:
10/12/2007
Publication #:
US20090100254
Pub Dt:
04/16/2009
Title:
DEBUG INSTRUCTION FOR USE IN A DATA PROCESSING SYSTEM
17
Patent #:
7870430
Issue Dt:
01/11/2011
Application #:
12040215
Filing Dt:
02/29/2008
Publication #:
US20090222692
Pub Dt:
09/03/2009
Title:
METHOD AND APPARATUS FOR SHARING DEBUG RESOURCES
18
Patent #:
7870434
Issue Dt:
01/11/2011
Application #:
12040221
Filing Dt:
02/29/2008
Publication #:
US20090222693
Pub Dt:
09/03/2009
Title:
METHOD AND APPARATUS FOR MASKING DEBUG RESOURCES
19
Patent #:
NONE
Issue Dt:
Application #:
12112580
Filing Dt:
04/30/2008
Publication #:
US20090276587
Pub Dt:
11/05/2009
Title:
SELECTIVELY PERFORMING A SINGLE CYCLE WRITE OPERATION WITH ECC IN A DATA PROCESSING SYSTEM
20
Patent #:
7814300
Issue Dt:
10/12/2010
Application #:
12112583
Filing Dt:
04/30/2008
Publication #:
US20090276609
Pub Dt:
11/05/2009
Title:
CONFIGURABLE PIPELINE TO PROCESS AN OPERATION AT ALTERNATE PIPELINE STAGES DEPENDING ON ECC / PARITY PROTECTION MODE OF MEMORY ACCESS
21
Patent #:
8190860
Issue Dt:
05/29/2012
Application #:
12872771
Filing Dt:
08/31/2010
Publication #:
US20100332940
Pub Dt:
12/30/2010
Title:
RESULT FORWARDING TO DEPENDENT INSTRUCTION IN PIPELINED PROCESSOR WITH MODE SELECTABLE EXECUTION IN E1 OR E2 PIPELINED OPERATIONAL STAGES
Assignor
1
FREESCALE SEMICONDUCTOR, INC.
Exec Dt:
07/29/2011
Assignee
1
RAMBUS INC.
1050 ENTERPRISE WAY, SUITE 700
SUNNYVALE, CALIFORNIA 94089
Correspondence name and address
F. LESLIE BESSENGER III
FINNEGAN, HENDERSON, FARABOW, GARRETT, ET AL
901 NEW YORK AVENUE, N.W.
WASHINGTON, D.C. 20001-4413

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