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Patent Assignment Details

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Reel/Frame:	027171/0635			Pages:	6
		Recorded:	11/03/2011
Attorney Dkt #:	RPXC-29189 (G-LINK)
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 13

Patent #:	6033945	Issue Dt:	03/07/2000	Application #:	09089928	Filing Dt:	06/03/1998
Title:	MULTIPLE EQUILIBRATION CIRCUITS FOR A SINGLE BIT LINE

Patent #:	6031784	Issue Dt:	02/29/2000	Application #:	09148817	Filing Dt:	09/04/1998
Title:	HIERARCHICAL DECODING OF A MEMORY DEVICE

Patent #:	5970020	Issue Dt:	10/19/1999	Application #:	09154664	Filing Dt:	09/16/1998
Title:	CONTROLLING THE SET UP OF A MEMORY ADDRESS

Patent #:	6166976	Issue Dt:	12/26/2000	Application #:	09418959	Filing Dt:	10/15/1999
Title:	MULTIPLE EQUILIBRATION CIRCUITS FOR A SINGLE BIT LINE

Patent #:	6275441	Issue Dt:	08/14/2001	Application #:	09588994	Filing Dt:	06/06/2000
Title:	Data input/output system for multiple data rate memory devices

Patent #:	6501670	Issue Dt:	12/31/2002	Application #:	09607802	Filing Dt:	06/30/2000
Title:	HIGH SPEED MEMORY ARCHITECTURE AND BUSING

Patent #:	6496032	Issue Dt:	12/17/2002	Application #:	09608674	Filing Dt:	06/29/2000
Title:	METHOD AND STRUCTURE FOR EFFICIENTLY PLACING AND INTERCONNECTING CIRCUIT BLOCKS IN AN INTEGRATED CIRCUIT

Patent #:	6445641	Issue Dt:	09/03/2002	Application #:	09654147	Filing Dt:	09/01/2000
Title:	MEMORY DEVICE WITH TIME SHARED DATA LINES

Patent #:	6765976	Issue Dt:	07/20/2004	Application #:	09660860	Filing Dt:	09/13/2000
Title:	DELAY-LOCKED LOOP FOR DIFFERENTIAL CLOCK SIGNALS

Patent #:	NONE	Issue Dt:		Application #:	09757023	Filing Dt:	01/08/2001
Publication #:	US20030034816	Pub Dt:	02/20/2003
Title:	Delay-locked loop for differential clock signals

Patent #:	6606272	Issue Dt:	08/12/2003	Application #:	09823325	Filing Dt:	03/29/2001
Publication #:	US20020141251	Pub Dt:	10/03/2002
Title:	METHOD AND CIRCUIT FOR PROCESSING OUTPUT DATA IN PIPELINED CIRCUITS

Patent #:	6529428	Issue Dt:	03/04/2003	Application #:	09863151	Filing Dt:	05/22/2001
Publication #:	US20020176294	Pub Dt:	11/28/2002
Title:	MULTI-BIT PARALLEL TESTING FOR MEMORY DEVICES

Patent #:	7027344	Issue Dt:	04/11/2006	Application #:	10804461	Filing Dt:	03/18/2004
Title:	HIGH-SPEED SEMICONDUCTOR MEMORY HAVING INTERNAL REFRESH CONTROL

Assignor

Exec Dt:

10/25/2011

Assignee

ONE MARKET PLAZA, STEUART TOWER, SUITE 700

SAN FRANCISCO, CALIFORNIA 94105

Correspondence name and address
	GREGORY M. HOWISON
	P.O. BOX 741715
	DALLAS, TX 75374-1715

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