Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 027213/0485 | |
| Pages: | 3 |
| | Recorded: | 11/11/2011 | | |
Attorney Dkt #: | NEX-33827 & NEX-33828 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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06/22/2010
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Application #:
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11989487
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Filing Dt:
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01/25/2008
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Publication #:
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Pub Dt:
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10/15/2009
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Title:
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TEST VECTOR GENERATING METHOD AND TEST VECTOR GENERATING PROGRAM OF SEMICONDUCTOR LOGIC CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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08/16/2011
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Application #:
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12597106
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Filing Dt:
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10/22/2009
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Publication #:
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Pub Dt:
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04/15/2010
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Title:
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TEST PATTERN GENERATION METHOD FOR AVOIDING FALSE TESTING IN TWO-PATTERN TESTING FOR SEMICONDUCTOR INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/19/2013
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Application #:
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12761643
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Filing Dt:
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04/16/2010
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Publication #:
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Pub Dt:
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08/26/2010
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Title:
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DON'T-CARE-BIT IDENTIFICATION METHOD AND DON'T-CARE-BIT IDENTIFICATION PROGRAM
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Patent #:
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Issue Dt:
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05/28/2013
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Application #:
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12761654
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Filing Dt:
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04/16/2010
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Publication #:
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Pub Dt:
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08/12/2010
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Title:
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TARGET LOGIC VALUE DETERMINATION METHOD FOR UNSPECIFIED BIT IN TEST VECTOR FOR COMBINATIONAL CIRCUIT AND NON-TRANSITORY COMPUTER-READABLE MEDIUM
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Assignee
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11-13 MINAMI-AOYAMA 2-CHOME |
MINTO-KU, TOKYO, JAPAN 107-0062 |
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Correspondence name and address
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RANKIN, HILL & CLARK
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23755 LORAIN ROAD
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SUITE 200
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NORTH OLMSTED, OH 44070
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