Patent Assignment Details
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| Reel/Frame: | 027312/0409 | |
| Pages: | 6 |
| | Recorded: | 12/01/2011 | | |
| Attorney Dkt #: | Q126613 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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06/04/2013
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Application #:
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13262759
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Filing Dt:
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12/01/2011
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Publication #:
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Pub Dt:
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04/19/2012
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS AND METHOD FOR ANALYZING A DELAY IN A SEMICONDUCTOR INTEGRATED CIRCUIT
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Assignees
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| 7-1, SHIBA 5-CHOME |
| MINATO-KU, TOKYO, JAPAN 108-8001 |
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| 1753, SHIMONUMABE, NAKAHARA-KU |
| KAWASAKI-SHI, KANAGAWA, JAPAN 211-8668 |
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Correspondence name and address
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SUGHRUE MION PLLC
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2100 PENNSYLVANIA AVE NW
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SUITE 800
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WASHINGTON, DC 20037
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