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Reel/Frame:027560/0411   Pages: 11
Recorded: 01/19/2012
Attorney Dkt #:252016-9000
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 67
1
Patent #:
Issue Dt:
07/28/1998
Application #:
08738214
Filing Dt:
10/25/1996
Title:
INTEGRATED CIRCUIT OUTPUT DRIVER INCORPORATING POWER DISTRIBUTION NOISE SUPPRESSION CIRCUITRY
2
Patent #:
Issue Dt:
02/08/2000
Application #:
08891973
Filing Dt:
07/11/1997
Title:
ADJUSTABLE, FULL CMOS INPUT BUFFER FOR TTL, CMOS, OR LOW SWING INPUT PROTOCOLS
3
Patent #:
Issue Dt:
07/06/1999
Application #:
08892216
Filing Dt:
07/14/1997
Title:
AN RC DELAY CIRCUIT FOR INTEGRATED CIRCUITS
4
Patent #:
Issue Dt:
08/18/1998
Application #:
08893641
Filing Dt:
07/11/1997
Title:
NEW BANDGAP REFERENCE CIRCUIT
5
Patent #:
Issue Dt:
02/02/1999
Application #:
08893642
Filing Dt:
07/11/1997
Title:
SEMICONDUCTOR MEMORY WITH A NOVEL COLUMN DECODER FOR SELECTING A REDUNDANT ARRAY
6
Patent #:
Issue Dt:
02/02/1999
Application #:
08944571
Filing Dt:
10/06/1997
Title:
LOCAL WORD LINE DECORDER FOR MEMORY WITH 2 MOS DEVICES
7
Patent #:
Issue Dt:
04/20/1999
Application #:
08944771
Filing Dt:
10/06/1997
Title:
LOCAL WORD LINE DECODER FOR MEMORY WITH 2 1/2 MOS DEVICES
8
Patent #:
Issue Dt:
08/18/1998
Application #:
08958205
Filing Dt:
10/17/1997
Title:
SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED READ SIGNAL GENERATION OF DATA LINES AND ASSISTED PRECHARGE TO MID-LEVEL
9
Patent #:
Issue Dt:
12/29/1998
Application #:
08968155
Filing Dt:
11/17/1997
Title:
METHOD OF FORMING A NEW BIPOLAR/CMOS PIXEL FOR HIGH RESOLUTION IMAGERS
10
Patent #:
Issue Dt:
04/18/2000
Application #:
08995379
Filing Dt:
12/22/1997
Title:
HIGH-SPEED SYNCHRONOUS WRITE CONTROL SCHEME
11
Patent #:
Issue Dt:
02/06/2001
Application #:
09030197
Filing Dt:
02/25/1998
Title:
MULIPLE-BIT, CURRENT MODE DATA BUS
12
Patent #:
Issue Dt:
10/17/2000
Application #:
09036726
Filing Dt:
03/06/1998
Title:
CROW-BAR CURRENT REDUCTION CIRCUIT
13
Patent #:
Issue Dt:
05/16/2000
Application #:
09044198
Filing Dt:
03/17/1998
Title:
MULTIPLE INPUT/OUTPUT LEVEL INTERFACE INPUT RECEIVER
14
Patent #:
Issue Dt:
03/21/2000
Application #:
09044205
Filing Dt:
03/17/1998
Title:
INPUT RECEIVER FOR LIMITING CURRENT DURING RELIABILITY SCREENING
15
Patent #:
Issue Dt:
01/18/2000
Application #:
09046408
Filing Dt:
03/23/1998
Title:
REGULATOR SYSTEM FOR AN ON-CHIP SUPPLY VOLTAGE GENERATOR
16
Patent #:
Issue Dt:
01/16/2001
Application #:
09047540
Filing Dt:
03/25/1998
Title:
EDGE TRIGGERED DELAY LINE, A MUTIPLE ADJUSTABLE DELAY LINE CIRCUIT, AND AN APPLICATION OF SAME
17
Patent #:
Issue Dt:
08/29/2000
Application #:
09047541
Filing Dt:
03/25/1998
Title:
CLOCK SYNCHRONIZED DELAY SCHEME USING EDGE-TRIGGERED DELAY LINES AND LATCHES WITH ONE CLOCK LOCK TIME
18
Patent #:
Issue Dt:
05/16/2000
Application #:
09053854
Filing Dt:
04/02/1998
Title:
OPERATION METHODS FOR ACTIVE BICMOS PIXEL FOR ELECTRONIC SHUTTER AND IMAGE-LAG ELIMINATION
19
Patent #:
Issue Dt:
10/26/1999
Application #:
09056546
Filing Dt:
04/07/1998
Title:
METHOD AND CIRCUIT FOR DISABLING A TWO-PHASE CHARGE PUMP
20
Patent #:
Issue Dt:
04/18/2000
Application #:
09063997
Filing Dt:
04/21/1998
Title:
APPARATUS FOR GENERATING A TIMING SIGNAL
21
Patent #:
Issue Dt:
09/05/2006
Application #:
09064884
Filing Dt:
04/20/1998
Title:
DYNAMICALLY ADJUSTABLE ON-CHIP SUPPLY VOLTAGE GENERATION
22
Patent #:
Issue Dt:
08/29/2000
Application #:
09071601
Filing Dt:
05/01/1998
Title:
TIMING CIRCUIT THAT SELECTIVELY TRIGGERS ON A RISING OR FALLING INPUT SIGNAL EDGE
23
Patent #:
Issue Dt:
10/24/2000
Application #:
09075745
Filing Dt:
05/11/1998
Title:
AN EPROM USED AS A VOLTAGE MONITOR FOR SEMICONDUCTOR BURN-IN
24
Patent #:
Issue Dt:
08/08/2000
Application #:
09080115
Filing Dt:
05/18/1998
Title:
ELECTRICALLY PROGRAMMABLE FUSE
25
Patent #:
Issue Dt:
01/18/2000
Application #:
09085332
Filing Dt:
05/26/1998
Title:
ANTIFUSE PROGRAMMING AND DETECTING CIRCUIT
26
Patent #:
Issue Dt:
07/18/2000
Application #:
09085613
Filing Dt:
05/27/1998
Title:
NEW SCHMITT TRIGGER INPUT STAGE
27
Patent #:
Issue Dt:
12/07/1999
Application #:
09103676
Filing Dt:
06/23/1998
Title:
DISTRIBUTED ARRAY ACTIVATION ARRANGEMENT
28
Patent #:
Issue Dt:
09/07/1999
Application #:
09120360
Filing Dt:
07/22/1998
Title:
BIAS SCHEME TO REDUCE BURN-IN TEST TIME FOR SEMICONDUCTOR MEMORY WHILE PREVENTING JUNCTION BREAKDOWN
29
Patent #:
Issue Dt:
05/09/2000
Application #:
09135252
Filing Dt:
08/17/1998
Title:
MULTIPLE DATA CLOCK ACTIVATION WITH PROGRAMMABLE DELAY FOR USE IN MULTIPLE CAS LATENCY MEMORY DEVICES
30
Patent #:
Issue Dt:
01/25/2000
Application #:
09156183
Filing Dt:
09/17/1998
Title:
MOCK WORDLINE SCHEME FOR TIMING CONTROL
31
Patent #:
Issue Dt:
11/13/2001
Application #:
09177341
Filing Dt:
10/23/1998
Title:
METHOD TO TEST AUTO-REFRESH AND SELF REFRESH CIRCUITRY
32
Patent #:
Issue Dt:
12/26/2000
Application #:
09189439
Filing Dt:
11/10/1998
Title:
METHOD AND APPARATUS OF AN OUTPUT BUFFER FOR CONTROLLING THE GROUND BOUNCE OF A SEMICONDUCTOR DEVICE
33
Patent #:
Issue Dt:
05/29/2001
Application #:
09222271
Filing Dt:
12/28/1998
Title:
ENHANCED RANDOM NUMBER GENERATOR
34
Patent #:
Issue Dt:
03/27/2001
Application #:
09262503
Filing Dt:
03/04/1999
Title:
INTERNAL CHARGE PUMP VOLTAGE LIMIT CONTROL
35
Patent #:
Issue Dt:
05/09/2000
Application #:
09266006
Filing Dt:
03/12/1999
Title:
ON-CHIP-GENERATED SUPPLY VOLTAGE REGULATOR WITH POWER-UP MODE
36
Patent #:
Issue Dt:
06/18/2002
Application #:
09274211
Filing Dt:
03/23/1999
Title:
SWITCH LEVEL SIMULATION WITH CROSS-COUPLED DEVICES
37
Patent #:
Issue Dt:
08/29/2000
Application #:
09292660
Filing Dt:
04/15/1999
Title:
ANY VALUE, TEMPERATURE INDEPENDENT, VOLTAGE REFERENCE UTILIZING BAND-GAP VOLTAGE REFERENCE AND CASCODE CURRENT MIRROR CIRCUITS
38
Patent #:
Issue Dt:
02/27/2001
Application #:
09320427
Filing Dt:
05/26/1999
Title:
TIMING CIRCUIT FOR A BURST-MODE ADDRESS COUNTER
39
Patent #:
Issue Dt:
11/21/2000
Application #:
09358013
Filing Dt:
07/21/1999
Title:
DEVICE AND METHOD FOR GENERATING A VARIABLE DUTY CYCLE CLOCK
40
Patent #:
Issue Dt:
05/21/2002
Application #:
09400353
Filing Dt:
09/20/1999
Title:
LOW POWER HIGH-SPEED BUS RECEIVER
41
Patent #:
Issue Dt:
02/06/2001
Application #:
09422022
Filing Dt:
10/20/1999
Title:
LAYOUT FOR PULL-UP/PULL DOWN DEVICES OF OFF-CHIP DRIVER
42
Patent #:
Issue Dt:
05/08/2001
Application #:
09429402
Filing Dt:
10/28/1999
Title:
SEMICONDUCTOR MEMORY DEVICE WITH FUNCTION OF EQUALIZING VOLTAGE OF DATALINE PAIR
43
Patent #:
Issue Dt:
12/26/2000
Application #:
09429595
Filing Dt:
10/28/1999
Title:
DYNAMIC PRECHARGE REDUNDANT CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE
44
Patent #:
Issue Dt:
01/01/2002
Application #:
09498982
Filing Dt:
02/07/2000
Title:
Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols
45
Patent #:
Issue Dt:
06/12/2001
Application #:
09498985
Filing Dt:
02/07/2000
Title:
Self-refresh test time reduction scheme
46
Patent #:
Issue Dt:
05/22/2001
Application #:
09548032
Filing Dt:
04/12/2000
Title:
Redundant decoder having fuse-controlled transistor
47
Patent #:
Issue Dt:
05/21/2002
Application #:
09621373
Filing Dt:
07/21/2000
Title:
Electrically programmable fuse
48
Patent #:
Issue Dt:
09/04/2001
Application #:
09621374
Filing Dt:
07/21/2000
Title:
Electrically programmable fuse
49
Patent #:
Issue Dt:
07/17/2001
Application #:
09633645
Filing Dt:
08/07/2000
Title:
Bias monitor for semiconductor burn-in
50
Patent #:
Issue Dt:
05/07/2002
Application #:
09640533
Filing Dt:
08/17/2000
Title:
CLOCK DUTY CYCLE CORRECTION CIRCUIT
51
Patent #:
Issue Dt:
12/04/2001
Application #:
09670405
Filing Dt:
09/28/2000
Title:
Local bit switch decode circuit and method
52
Patent #:
Issue Dt:
03/23/2004
Application #:
09670685
Filing Dt:
09/27/2000
Title:
METHOD AND APPARATUS FOR DARK LEVEL INTEGRATION OF IMAGE SENSOR WITHOUT INTEGRATING BAD PIXELS
53
Patent #:
Issue Dt:
07/27/2004
Application #:
09671565
Filing Dt:
09/27/2000
Title:
METHOD OF BAD PIXEL CORRECTION
54
Patent #:
Issue Dt:
11/04/2003
Application #:
09671566
Filing Dt:
09/27/2000
Title:
METHOD DEFECTIVE PIXEL ADDRESS DETECTION FOR IMAGE SENSORS HAVING WINDOWING FUNCTION
55
Patent #:
Issue Dt:
02/28/2006
Application #:
09671567
Filing Dt:
09/27/2000
Title:
METHOD OF DEFECTIVE PIXEL ADDRESS DETECTION FOR IMAGE SENSORS
56
Patent #:
Issue Dt:
11/20/2001
Application #:
09709590
Filing Dt:
11/13/2000
Title:
Multiple-bit, current mode data bus
57
Patent #:
Issue Dt:
10/09/2001
Application #:
09709598
Filing Dt:
11/13/2000
Title:
Multiple-bit, current mode data bus
58
Patent #:
Issue Dt:
12/11/2001
Application #:
09747233
Filing Dt:
12/26/2000
Title:
Test mode for verification of on-chip generated row addresses
59
Patent #:
Issue Dt:
07/20/2004
Application #:
09764243
Filing Dt:
01/19/2001
Title:
RETICLE OPTION LAYER DETECTION METHOD
60
Patent #:
Issue Dt:
03/29/2005
Application #:
09802458
Filing Dt:
03/09/2001
Publication #:
Pub Dt:
09/12/2002
Title:
METHOD OF BUFFER MANAGEMENT AND TASK SCHEDULING FOR TWO-DIMENSIONAL DATA TRANSFORMING
61
Patent #:
Issue Dt:
11/18/2003
Application #:
09876595
Filing Dt:
06/08/2001
Publication #:
Pub Dt:
03/14/2002
Title:
EPROM USED AS A VOLTAGE MONITOR FOR SEMICONDUCTOR BURN-IN
62
Patent #:
Issue Dt:
10/25/2005
Application #:
09886776
Filing Dt:
06/21/2001
Publication #:
Pub Dt:
02/14/2002
Title:
METHOD AND APPARATUS OF CONTROLLING A PIXEL RESET LEVEL FOR REDUCING AN IMAGE LAG IN A CMOS SENSOR
63
Patent #:
Issue Dt:
04/25/2006
Application #:
09896426
Filing Dt:
06/29/2001
Publication #:
Pub Dt:
02/10/2005
Title:
PIXEL DEFECT CORRECTION IN A CMOS ACTIVE PIXEL IMAGE SENSOR
64
Patent #:
Issue Dt:
09/28/2004
Application #:
09896486
Filing Dt:
06/29/2001
Title:
ON-CHIP DESIGN-FOR-TESTING STRUCTURE FOR CMOS APS (ACTIVE PIXEL SENSOR) IMAGE SENSOR
65
Patent #:
Issue Dt:
05/06/2008
Application #:
11480378
Filing Dt:
07/05/2006
Publication #:
Pub Dt:
01/10/2008
Title:
VOLTAGE CONVERTER
66
Patent #:
Issue Dt:
07/13/2010
Application #:
11636524
Filing Dt:
12/11/2006
Publication #:
Pub Dt:
06/12/2008
Title:
STATIC RANDOM ACCESS MEMORY
67
Patent #:
Issue Dt:
06/15/2010
Application #:
11833160
Filing Dt:
08/02/2007
Publication #:
Pub Dt:
02/05/2009
Title:
VOLTAGE REGULATOR
Assignor
1
Exec Dt:
12/31/2011
Assignee
1
NO.8, LI-HSIN ROAD. 6, SCIENCE-BASED INDUSTRIAL PARK
HSIN-CHU, TAIWAN 300-77
Correspondence name and address
THOMAS, KAYDEN, HORSTEMEYER & RISLEY, LL
400 INTERSTATE NORTH PARKWAY SE
SUITE 1500
ATLANTA, GA 30339

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