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Patent #:
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Issue Dt:
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08/08/1995
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Application #:
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07726893
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Filing Dt:
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07/08/1991
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Title:
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MICROPROCESSOR ARCHITECTURE WITH A SWITCH NETWORK FOR DATA TRANSFER BETWEEN CACHE, MEMORY PORT, AND IOU
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Patent #:
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Issue Dt:
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11/09/1993
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Application #:
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07805838
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Filing Dt:
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12/13/1991
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Title:
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SEMAPHORE BYPASS
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Patent #:
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Issue Dt:
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09/06/1994
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Application #:
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07833419
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Filing Dt:
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02/10/1992
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Title:
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METHOD FOR GENERATING POWER SLITS
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Patent #:
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Issue Dt:
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10/27/1998
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Application #:
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07846231
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Filing Dt:
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03/06/1992
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Title:
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SYSTEM AND METHOD FOR REDUCING THE CRITICAL PATH IN MEMORY CONTROL INPUT/OUTPUT CONTROL UNIT OPERATIONS
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Patent #:
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Issue Dt:
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03/14/1995
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Application #:
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07846237
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Filing Dt:
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03/05/1992
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Title:
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REGISTER FILE BACKUP QUEUE
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Patent #:
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Issue Dt:
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09/19/1995
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Application #:
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07860717
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Filing Dt:
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03/31/1992
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Title:
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SELECTIVE POWER-DOWN FOR HIGH PERFORMANCE CPU/SYSTEM
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Patent #:
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Issue Dt:
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12/06/1994
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Application #:
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07860718
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Filing Dt:
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03/31/1992
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Title:
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SEMICONDUCTOR FLOOR PLAN FOR A REGISTER RENAMING CIRCUIT
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Patent #:
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Issue Dt:
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08/22/1995
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Application #:
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07862623
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Filing Dt:
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03/31/1992
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Title:
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A SYSTEM AND METHOD FOR TRANSFERRING DATA BETWEEN A PLURALITY OF VIRTUAL FIFOS AND A PERIPHERAL VIA A HARDWARE FIFO AND SELECTIVELY UPDATING CONTRO INFORMATION ASSOCIATED WITH THE VIRTUAL FIFOS
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Patent #:
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Issue Dt:
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06/28/1994
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Application #:
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07877562
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Filing Dt:
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05/01/1992
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Title:
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AREA-EFFICIENT MULTIPLIER FOR USE IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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10/05/1993
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Application #:
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07887511
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Filing Dt:
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05/22/1992
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Title:
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LOW-POWER AREA-EFFICIENT ABSOLUTE VALUE ARITHMETIC UNIT
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Patent #:
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Issue Dt:
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05/25/1993
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Application #:
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07897729
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Filing Dt:
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06/12/1992
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Title:
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SYSTEM AND METHOD FOR REDUCING GROUND BOUNCE IN INTEGRATED CIRCUIT OUTPUT BUFFERS
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Patent #:
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Issue Dt:
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08/29/1995
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Application #:
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07968901
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Filing Dt:
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10/30/1992
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Title:
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POLYGON RASTERIZATION
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Patent #:
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Issue Dt:
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08/08/1995
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Application #:
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07972699
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Filing Dt:
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11/06/1992
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Title:
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SYSTEM AND METHOD FOR SYNCHRONIZING PROCESSORS IN A PARALLEL PROCESSING ENVIRONMENT
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Patent #:
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Issue Dt:
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06/27/1995
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Application #:
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07973344
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Filing Dt:
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11/09/1992
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Title:
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SYSTEM AND METHOD FOR SUPPORTING CONTEXT SWITCHING WITHIN A MULTIPROCESSOR SYSTEM HAVING FUNCTIONAL BLOCKS THAT GENERATE STATE PROGRAMS WITH CODED REGISTER LOAD INSTRUCTIONS
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Patent #:
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Issue Dt:
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03/12/1996
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Application #:
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07997943
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Filing Dt:
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12/31/1992
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Title:
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INPUT OUTPUT CONTROL UNIT HAVING DEDICATED PATHS FOR CONTROLLING THE INPUT AND OUTPUT OF DATA BETWEEN HOST PROCESSOR AND EXTERNAL DEVICE
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Patent #:
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Issue Dt:
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02/18/1997
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Application #:
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07999648
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Filing Dt:
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12/31/1992
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Title:
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SYSTEM AND METHOD FOR ASSIGNING TAGS TO INSTRUCTIONS TO CONTROL INSTRUCTION EXECUTION
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Patent #:
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Issue Dt:
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10/26/1993
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Application #:
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08046716
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Filing Dt:
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04/16/1993
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Title:
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AREA-EFFICIENT MULTIPLIER FOR USE IN AN INTEGRTED CIRCUIT
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Patent #:
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Issue Dt:
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09/05/1995
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Application #:
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08065063
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Filing Dt:
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05/24/1993
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Title:
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RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING FAST TRAP AND EXCEPTION STATE
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Patent #:
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Issue Dt:
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07/02/1996
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Application #:
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08141966
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Filing Dt:
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10/28/1993
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Title:
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PIXEL MODIFICATION UNIT FOR USE AS A FUNCTIONAL UNIT IN A SUPERSCALAR MICROPROCESSOR
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Patent #:
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Issue Dt:
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05/06/1997
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Application #:
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08224328
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Filing Dt:
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04/04/1994
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Title:
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SYSTEM AND METHOD FOR ASSIGNING TAGS TO CONTROL INSTRUCTION PROCESSING IN A SUPERSCALAR PROCESSOR
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Patent #:
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Issue Dt:
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08/22/1995
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Application #:
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08255910
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Filing Dt:
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06/08/1994
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Title:
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CLOCK GENERATOR WITH PROGRAMMABLE NON-OVERLAPPING CLOCK EDGE CAPABILITY
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Patent #:
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Issue Dt:
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02/28/1995
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Application #:
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08267646
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Filing Dt:
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06/28/1994
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Title:
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PAGE PRINTER CONTROLLER INCLUDING A SINGLE CHIP SUPERSCALAR MICROPROCESSOR WITH GRAPHICS FUNCTIONAL UNITS
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Patent #:
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Issue Dt:
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10/24/1995
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Application #:
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08289278
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Filing Dt:
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08/11/1994
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Title:
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A POWER BUS HAVING POWER SLITS EMBODIED THEREIN
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Patent #:
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Issue Dt:
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10/01/1996
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Application #:
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08310821
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Filing Dt:
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09/22/1994
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Title:
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Z-BUFFER TAG MEMORY ORGANIZATION
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Patent #:
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Issue Dt:
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01/14/1997
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Application #:
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08317839
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Filing Dt:
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10/05/1994
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Title:
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A SYSTEM FOR TRANSFERRING DATA ONTO BUSES HAVING DIFFERENT WIDTHS
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Patent #:
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Issue Dt:
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12/03/1996
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Application #:
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08325946
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Filing Dt:
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10/19/1994
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Title:
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INTEGRATED CIRCUIT DEVICE IMPLEMENTED USING A PLURALITY OF PARTIALLY DEFECTIVE INTEGRATED CIRCUIT CHIPS
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Patent #:
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Issue Dt:
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01/02/1996
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Application #:
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08345333
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Filing Dt:
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11/21/1994
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Title:
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RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING FAST TRAP AND EXCEPTION STATE
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Patent #:
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Issue Dt:
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12/03/1996
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Application #:
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08352680
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Filing Dt:
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11/30/1994
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Title:
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AN APPARATUS AND METHOD FOR EMULATING A MICROELECTRONIC DEVICE BY INTERCONNECTING AND RUNNING TEST VECTORS ON PHYSICALLY IMPLEMENTED FUNCTIONAL MODULES
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Patent #:
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Issue Dt:
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10/15/1996
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Application #:
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08353299
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Filing Dt:
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12/05/1994
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Title:
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INTEGRATED STRUCTURE LAYOUT AND LAYOUT OF INTERCONNECTIONS FOR AN INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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05/13/1997
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Application #:
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08357166
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Filing Dt:
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12/13/1994
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Title:
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HIGH DENSITY BUFFER ARCHITECTURE AND METHOD
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Patent #:
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Issue Dt:
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05/07/1996
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Application #:
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08366423
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Filing Dt:
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12/29/1994
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Title:
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GRAPHICS CONTROL PLANES FOR WINDOWING AND OTHER DISPLAY OPERATIONS
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Patent #:
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Issue Dt:
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09/24/1996
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Application #:
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08383015
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Filing Dt:
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02/03/1995
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Title:
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PAGE PRINTER CONTROLLER INCLUDING A SINGLE CHIP SUPERSCALAR MICROPROCESSOR WITH GRAPHICS FUNCTIONAL UNITS
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Patent #:
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Issue Dt:
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09/24/1996
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Application #:
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08397016
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Filing Dt:
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03/01/1995
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Title:
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HIGH-PERFORMANCE, SUPERSCALAR-BASED COMPUTER SYSTEM WITH OUT-OF-ORDER INSTRUCTION EXECUTION AND CONCURRENT RESULTS DISTRIBUTION
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Patent #:
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Issue Dt:
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12/24/1996
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Application #:
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08403527
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Filing Dt:
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03/13/1995
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Title:
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REGISTER FILE BACKUP QUEUE
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Patent #:
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Issue Dt:
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07/15/1997
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Application #:
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08413983
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Filing Dt:
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03/06/1995
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Title:
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HARDWARE ARCHITECTURE FOR IMAGE GENERATION AND MANIPULATION
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Patent #:
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Issue Dt:
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05/19/1998
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Application #:
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08442649
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Filing Dt:
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05/16/1995
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Title:
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MULTIMPROCESSOR SYSTEM HAVING DYNAMIC PRIORITY BASED ON ROW MATCH OF PREVIOUS SERVICED ADDRESS, NUMBER OF TIMES DENIED SERVICE AND NUMBER OF TIMES SERVICED WITHOUT INTERRUPTION
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Patent #:
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Issue Dt:
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10/01/1996
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Application #:
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08455133
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Filing Dt:
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05/31/1995
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Title:
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A POWER BUS HAVING POWER SLITS AND HOLES EMBODIED THEREIN, AND METHOD FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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10/08/1996
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Application #:
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08468083
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Filing Dt:
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06/06/1995
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Title:
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A COMPUTER SYSTEM INCLUDING A PAGE PRINTER CONTROLLER INCLUDING A SINGLE CHIP SUPERCALAR MICROPROCESSOR WITH GRAPHICAL FUNCTIONAL UNITS
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Patent #:
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Issue Dt:
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02/04/1997
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Application #:
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08469928
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Filing Dt:
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06/06/1995
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Title:
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HIGH DENSITY BUFFER MEMORY ARCHITECTURE
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Patent #:
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Issue Dt:
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02/18/1997
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Application #:
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08474385
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Filing Dt:
|
06/07/1995
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|
Title:
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MICROPROCESSOR ARCHITECTURE WITH A SWITCH NETWORK FOR DATA TRANSFER BETWEEN CACHE, MEMORY PORT, AND IOU
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|
|
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Patent #:
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|
Issue Dt:
|
12/31/1996
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Application #:
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08478531
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Filing Dt:
|
06/07/1995
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Title:
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SYSTEM AND METHOD FOR REGISTER RENAMING
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Patent #:
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Issue Dt:
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07/07/1998
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Application #:
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08479035
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Filing Dt:
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06/07/1995
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Title:
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SYSTEM AND METHOD FOR PROCESSING MULTIPLE REQUESTS AND OUT OF ORDER RETURNS
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Patent #:
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Issue Dt:
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10/20/1998
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Application #:
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08481146
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Filing Dt:
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06/07/1995
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Title:
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SYSTEM AND METHOD FOR RETIRING INSTRUCTIONS IN A SUPERSCALAR MICROPROCESSOR
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Patent #:
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|
Issue Dt:
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08/05/1997
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Application #:
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08487976
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Filing Dt:
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06/07/1995
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Title:
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SELECTIVE POWER-DOWN FOR HIGH PERFORMANCE CPU/SYSTEM
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Patent #:
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Issue Dt:
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07/15/1997
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Application #:
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08487993
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Filing Dt:
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06/07/1995
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Title:
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A SYSTEM FOR TRANSFERRING DATA USING VALUE IN HARDWARE FIFO'S UNUSED DATA START POINTER TO UPDATE VIRTUAL FIFO'S START ADDRESS POINTER FOR FAST CONTEXT SWITCHING
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Patent #:
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Issue Dt:
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03/10/1998
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Application #:
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08665846
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Filing Dt:
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06/19/1996
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Title:
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POWER BUS HAVING POWER SLITS EMBODIED THEREIN AND METHOD FOR MAKING THE SAME
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Patent #:
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|
Issue Dt:
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03/31/1998
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Application #:
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08673465
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Filing Dt:
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07/01/1996
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Title:
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SYSTEM AND METHOD FOR GENERATING SUPPLEMENTAL READY SIGNALS TO ELIMINATE WASTED CYCLES BETWEEN OPERATIONS
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Patent #:
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Issue Dt:
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09/15/1998
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Application #:
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08698211
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Filing Dt:
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08/15/1996
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Title:
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SYSTEM AND METHOD FOR REGISTER RENAMING
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Patent #:
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Issue Dt:
|
11/03/1998
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Application #:
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08716728
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Filing Dt:
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09/23/1996
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Title:
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HIGH-PERFORMANCE SUPERSCALAR-BASED COMPUTER SYSTEM WITH OUT-OF-ORDER INSTRUCTION EXECUTION AND CONCURRENT RESULTS DISTRIBUTION
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Patent #:
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Issue Dt:
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03/31/1998
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Application #:
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08730658
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Filing Dt:
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10/11/1996
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Title:
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INTEGRATED STRUCTURE LAYOUT AND LAYOUT OF INTERCONNECTIONS FOR AN INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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03/23/1999
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Application #:
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08757252
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Filing Dt:
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11/27/1996
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Title:
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SYSTEM FOR SUPPORTING A BUFFER MEMORY WHEREIN DATA IS STORED IN MULTIPLE DATA WIDTHS BASED UPON A SWITCH INTERFACE FOR DETECTING THE DIFFERENT BUS SIZES
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Patent #:
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Issue Dt:
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03/09/1999
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Application #:
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08771911
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Filing Dt:
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12/23/1996
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Title:
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REGISTER FILE BACKUP QUEUE
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Patent #:
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Issue Dt:
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10/12/1999
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Application #:
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08795363
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Filing Dt:
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02/04/1997
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Title:
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METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT WITH PROGRAMMABLE NON-OVERLAPPING-CLOCK-EDGE CAPABILITY
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Patent #:
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Issue Dt:
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04/06/1999
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Application #:
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08799462
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Filing Dt:
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02/13/1997
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Title:
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SYSTEM AND METHOD FOR ASSIGNING TAGS TO INSTRUCTIONS TO CONTROL INSTRUCTION EXECUTION
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Patent #:
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Issue Dt:
|
09/08/1998
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Application #:
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08800507
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Filing Dt:
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02/14/1997
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Title:
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SPACE SAVIING METHOD AND FLOOR PLAN FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING A HIGH DENSITY BUFFER MEMORY
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Patent #:
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Issue Dt:
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04/20/1999
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Application #:
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08811237
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Filing Dt:
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03/03/1997
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Title:
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SYSTEM AND METHOD FOR ASSIGNING TAGS TO CONTROL INSTRUCTION PROCESSING IN A SUPERSCALAR PROCESSOR
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Patent #:
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Issue Dt:
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07/28/1998
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Application #:
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08811238
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Filing Dt:
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03/03/1997
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Title:
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SELECTIVE POWER-DOWN FOR HIGH PERFORMANCE CPU/SYSTEM
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Patent #:
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Issue Dt:
|
08/04/1998
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Application #:
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08824421
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Filing Dt:
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03/26/1997
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Title:
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HARDWARE ARCHITECTURE FOR IMAGE GENERATION AND MANIPULATION
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Patent #:
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Issue Dt:
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04/20/1999
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Application #:
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08903496
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Filing Dt:
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07/30/1997
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Title:
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SYSTEM AND METHOD FOR GENERATING 3D COLOR IMAGES WITH SIMULATED LIGHT SOURCES
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Patent #:
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Issue Dt:
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08/24/1999
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Application #:
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08915913
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Filing Dt:
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08/21/1997
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Title:
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MICROPROCESSOR ARCHITECTURE WITH A SWITCH NETWORK AND AN ARBITRATION UNIT FOR CONTROLLING ACCESS TO MEMORY PORTS
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Patent #:
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Issue Dt:
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11/03/1998
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Application #:
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08980057
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Filing Dt:
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11/26/1997
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Title:
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INTEGRATED STRUCTURE LAYOUT AND LAYOUT OF INTERCONNECTIONS FOR AN INSTRUCTION EXECUTION UNIT OF AN INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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06/01/1999
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Application #:
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08997605
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Filing Dt:
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12/23/1997
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Title:
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METHOD FOR MANUFACTURING A POWER BUS ON A CHIP
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Patent #:
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Issue Dt:
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10/10/2000
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Application #:
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09009412
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Filing Dt:
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01/20/1998
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Title:
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SYSTEM AND METHOD FOR RETIRING APPROXIMATELY SIMULTANEOUSLY A GROUP OF INSTRUCTIONS IN A SUPERSCALAR MICROPROCESSOR
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09024134
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Filing Dt:
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02/17/1998
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Title:
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COMPUTER SYSTEM FOR PROCESSING MULTIPLE REQUESTS AND OUT OF ORDER RETURNS USING A REQUEST QUEUE
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09063059
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Filing Dt:
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04/21/1998
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Title:
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SYSTEM AND METHOD FOR REGISTER RENAMING
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09069335
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Filing Dt:
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04/29/1998
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Title:
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SELECTIVE POWER-DOWN FOR HIGH PERFORMANCE CPU/SYSTEM
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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09158568
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Filing Dt:
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09/22/1998
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Title:
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HIGH-PERFORMANCE SUPERSCALAR-BASED COMPUTER SYSTEM WITH OUT-OF-ORDER INSTRUCTION EXECUTION AND CONCURRENT RESULTS DISTRIBUTION
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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09173560
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Filing Dt:
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10/16/1998
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Title:
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INTEGRATED STRUCTURE LAYOUT AND LAYOUT OF INTERCONNECTIONS FOR AN INTEGRATED CIRCUIT CHIP
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Patent #:
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04/16/2002
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04/04/2000
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04/17/2001
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08/07/2001
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05/15/2001
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12/19/2000
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06/04/2002
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06/27/2000
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06/25/2002
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05/20/2003
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10/19/2000
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11/27/2001
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03/15/2001
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04/23/2002
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02/07/2002
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