Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 028792/0676 | |
| Pages: | 26 |
| | Recorded: | 08/15/2012 | | |
| Attorney Dkt #: | 3521.52 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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11/20/2012
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Application #:
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11616919
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Filing Dt:
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12/28/2006
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Publication #:
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Pub Dt:
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07/03/2008
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Title:
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INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING IMPROVED REACTION BARRIER LAYERS
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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12955429
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Filing Dt:
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11/29/2010
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Publication #:
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Pub Dt:
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03/24/2011
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Title:
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THROUGH SUBSTRATE VIA INCLUDING VARIABLE SIDEWALL PROFILE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13025678
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Filing Dt:
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02/11/2011
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Publication #:
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Pub Dt:
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06/02/2011
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Title:
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THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13244576
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Filing Dt:
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09/25/2011
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Publication #:
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Pub Dt:
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01/19/2012
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Title:
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INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS
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Patent #:
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Issue Dt:
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06/11/2013
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Application #:
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13357146
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Filing Dt:
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01/24/2012
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Publication #:
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Pub Dt:
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05/17/2012
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Title:
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GRAIN REFINEMENT BY PRECIPITATE FORMATION IN PB-FREE ALLOYS OF TIN
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Patent #:
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Issue Dt:
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12/25/2012
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Application #:
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13361232
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Filing Dt:
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01/30/2012
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Publication #:
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Pub Dt:
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05/24/2012
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Title:
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SOLDER INTERCONNECT PADS WITH CURRENT SPREADING LAYERS
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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13364804
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Filing Dt:
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02/02/2012
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Publication #:
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Pub Dt:
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05/31/2012
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Title:
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THROUGH SILICON VIA FOR USE IN INTEGRATED CIRCUIT CHIPS
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Patent #:
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Issue Dt:
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12/25/2012
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Application #:
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13365519
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Filing Dt:
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02/03/2012
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Publication #:
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Pub Dt:
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05/24/2012
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Title:
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SOLDER MOLD PLATES USED IN PACKAGING PROCESS AND METHOD OF MANUFACTURING SOLDER MOLD PLATES
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Assignee
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| 3050 ZANKER ROAD |
| SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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ALLSTON L. JONES
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425 SHERMAN AVENUE, SUITE 230
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PALO ALTO, CA 94306
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