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Reel/Frame:	028840/0001			Pages:	173
		Recorded:	08/23/2012
Attorney Dkt #:	3186.0000000 (GRANTED)
Conveyance:	SECURITY AGREEMENT

Total properties: 90

1

Patent #:	4716552	Issue Dt:	12/29/1987	Application #:	06717348	Filing Dt:	03/29/1985
Title:	METHOD AND APPARATUS FOR NON-DESTRUCTIVE ACCESS OF VOLATILE AND NON-VOLATILE DATA IN A SHADOW MEMORY ARRAY

2

Patent #:	8183619	Issue Dt:	05/22/2012	Application #:	09539458	Filing Dt:	03/30/2000
Title:	METHOD AND SYSTEM FOR PROVIDING CONTACT TO A FIRST POLYSILICON LAYER IN A FLASH MEMORY DEVICE

3

Patent #:	7964905	Issue Dt:	06/21/2011	Application #:	09591266	Filing Dt:	06/09/2000
Title:	ANTI-REFLECTIVE INTERPOLY DIELECTRIC

4

Patent #:	7670936	Issue Dt:	03/02/2010	Application #:	10273184	Filing Dt:	10/18/2002
Title:	NITRIDATION OF GATE OXIDE BY LASER PROCESSING

5

Patent #:	8044387	Issue Dt:	10/25/2011	Application #:	10885959	Filing Dt:	07/07/2004
Title:	SEMICONDUCTOR DEVICE BUILT ON PLASTIC SUBSTRATE

6

Patent #:	7672803	Issue Dt:	03/02/2010	Application #:	11006034	Filing Dt:	12/07/2004
Title:	INPUT OF TEST CONDITIONS AND OUTPUT GENERATION FOR BUILT-IN SELF TEST

7

Patent #:	7863128	Issue Dt:	01/04/2011	Application #:	11049855	Filing Dt:	02/04/2005
Title:	NON-VOLATILE MEMORY DEVICE WITH IMPROVED ERASE SPEED

8

Patent #:	7692236	Issue Dt:	04/06/2010	Application #:	11059139	Filing Dt:	02/15/2005
Title:	MULTIPLE DUAL BIT MEMORY INTEGRATED CIRCUIT SYSTEM

9

Patent #:	8012673	Issue Dt:	09/06/2011	Application #:	11068674	Filing Dt:	03/01/2005
Title:	PROCESSING A COPOLYMER TO FORM A POLYMER MEMORY CELL

10

Patent #:	7737019	Issue Dt:	06/15/2010	Application #:	11075999	Filing Dt:	03/08/2005
Title:	METHOD FOR CONTAINING A SILICIDED GATE WITHIN A SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY

11

Patent #:	8022468	Issue Dt:	09/20/2011	Application #:	11091519	Filing Dt:	03/29/2005
Title:	ULTRAVIOLET RADIATION BLOCKING INTERLAYER DIELECTRIC

12

Patent #:	7927723	Issue Dt:	04/19/2011	Application #:	11091524	Filing Dt:	03/29/2005
Title:	FILM STACKS TO PREVENT UV-INDUCED DEVICE DAMAGE

13

Patent #:	7776682	Issue Dt:	08/17/2010	Application #:	11110165	Filing Dt:	04/20/2005
Title:	ORDERED POROSITY TO DIRECT MEMORY ELEMENT FORMATION

14

Patent #:	7679129	Issue Dt:	03/16/2010	Application #:	11128389	Filing Dt:	05/13/2005
Title:	SYSTEM AND METHOD FOR IMPROVING OXIDE-NITRIDE-OXIDE (ONO) COUPLING IN A SEMICONDUCTOR DEVICE

15

Patent #:	7786003	Issue Dt:	08/31/2010	Application #:	11136569	Filing Dt:	05/25/2005
Title:	BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME

16

Patent #:	8148770	Issue Dt:	04/03/2012	Application #:	11165329	Filing Dt:	06/24/2005
Title:	MEMORY DEVICE WITH BURIED BIT LINE STRUCTURE

17

Patent #:	7985687	Issue Dt:	07/26/2011	Application #:	11186969	Filing Dt:	07/22/2005
Title:	SYSTEM AND METHOD FOR IMPROVING RELIABILITY IN A SEMICONDUCTOR DEVICE

18

Patent #:	8133801	Issue Dt:	03/13/2012	Application #:	11189875	Filing Dt:	07/27/2005
Title:	METHOD FOR FORMING A SEMICONDUCTING LAYER WITH IMPROVED GAP FILLING PROPERTIES

19

Patent #:	7678674	Issue Dt:	03/16/2010	Application #:	11211509	Filing Dt:	08/26/2005
Title:	MEMORY CELL DUAL POCKET IMPLANT

20

Patent #:	7957204	Issue Dt:	06/07/2011	Application #:	11229667	Filing Dt:	09/20/2005
Title:	FLASH MEMORY PROGRAMMING POWER REDUCTION

21

Patent #:	7994047	Issue Dt:	08/09/2011	Application #:	11286173	Filing Dt:	11/22/2005
Title:	INTEGRATED CIRCUIT CONTACT SYSTEM

22

Patent #:	8089110	Issue Dt:	01/03/2012	Application #:	11350556	Filing Dt:	02/09/2006
Title:	SWITCHABLE MEMORY DIODES BASED ON FERROELECTRIC/CONJUGATED POLYMER HETEROSTRUCTURES AND/OR THEIR COMPOSITES

23

Patent #:	7816203	Issue Dt:	10/19/2010	Application #:	11378464	Filing Dt:	03/16/2006
Title:	METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

24

Patent #:	8039391	Issue Dt:	10/18/2011	Application #:	11388976	Filing Dt:	03/27/2006
Title:	METHOD OF FORMING A CONTACT IN A SEMICONDUCTOR DEVICE WITH ENGINEERED PLASMA TREATMENT PROFILE OF BARRIER METAL LAYER

25

Patent #:	7884030	Issue Dt:	02/08/2011	Application #:	11408086	Filing Dt:	04/21/2006
Title:	GAP-FILLING WITH UNIFORM PROPERTIES

26

Patent #:	7732281	Issue Dt:	06/08/2010	Application #:	11410695	Filing Dt:	04/24/2006
Title:	METHODS FOR FABRICATING DUAL BIT FLASH MEMORY DEVICES

27

Patent #:	7696038	Issue Dt:	04/13/2010	Application #:	11412365	Filing Dt:	04/26/2006
Title:	METHODS FOR FABRICATING FLASH MEMORY DEVICES

28

Patent #:	8093646	Issue Dt:	01/10/2012	Application #:	11432495	Filing Dt:	05/12/2006
Title:	FLASH MEMORY DEVICE AND METHOD OF FORMING THE SAME WITH IMPROVED GATE BREAKDOWN AND ENDURANCE

29

Patent #:	7777218	Issue Dt:	08/17/2010	Application #:	11462525	Filing Dt:	08/04/2006
Title:	MEMORY CELL CONTAINING COPOLYMER CONTAINING DIARYLACETYLENE PORTION

30

Patent #:	8093680	Issue Dt:	01/10/2012	Application #:	11521219	Filing Dt:	09/14/2006
Title:	METAL-INSULATOR-METAL-INSULATOR-METAL (MIMIM) MEMORY DEVICE

31

Patent #:	7515478	Issue Dt:	04/07/2009	Application #:	11841468	Filing Dt:	08/20/2007
Publication #:	US20090052245	Pub Dt:	02/26/2009
Title:	CMOS LOGIC COMPATIBLE NON-VOLATILE MEMORY CELL STRUCTURE, OPERATION, AND ARRAY CONFIGURATION

32

Patent #:	7696017	Issue Dt:	04/13/2010	Application #:	12141180	Filing Dt:	06/18/2008
Title:	MEMORY DEVICE WITH A SELECTION ELEMENT AND A CONTROL LINE IN A SUBSTANTIALLY SIMILAR LAYER

33

Patent #:	8116151	Issue Dt:	02/14/2012	Application #:	12189746	Filing Dt:	08/11/2008
Publication #:	US20100037032	Pub Dt:	02/11/2010
Title:	MULTI-LEVEL STORAGE ALGORITHM TO EMPHASIZE DISTURB CONDITIONS

34

Patent #:	8117521	Issue Dt:	02/14/2012	Application #:	12198381	Filing Dt:	08/26/2008
Publication #:	US20100058151	Pub Dt:	03/04/2010
Title:	IMPLEMENTATION OF RECYCLING UNUSED ECC PARITY BITS DURING FLASH MEMORY PROGRAMMING

35

Patent #:	7998846	Issue Dt:	08/16/2011	Application #:	12209478	Filing Dt:	09/12/2008
Publication #:	US20100065940	Pub Dt:	03/18/2010
Title:	3-D INTEGRATED CIRCUIT SYSTEM AND METHOD

36

Patent #:	7907455	Issue Dt:	03/15/2011	Application #:	12234733	Filing Dt:	09/22/2008
Publication #:	US20100074004	Pub Dt:	03/25/2010
Title:	HIGH VT STATE USED AS ERASE CONDITION IN TRAP BASED NOR FLASH CELL DESIGN

37

Patent #:	7804713	Issue Dt:	09/28/2010	Application #:	12234734	Filing Dt:	09/22/2008
Publication #:	US20100074005	Pub Dt:	03/25/2010
Title:	EEPROM EMULATION IN FLASH DEVICE

38

Patent #:	7791954	Issue Dt:	09/07/2010	Application #:	12234736	Filing Dt:	09/22/2008
Publication #:	US20100074006	Pub Dt:	03/25/2010
Title:	DYNAMIC ERASE STATE IN FLASH DEVICE

39

Patent #:	8004888	Issue Dt:	08/23/2011	Application #:	12234737	Filing Dt:	09/22/2008
Publication #:	US20100074007	Pub Dt:	03/25/2010
Title:	FLASH MIRROR BIT ARCHITECTURE USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL

40

Patent #:	7864596	Issue Dt:	01/04/2011	Application #:	12234738	Filing Dt:	09/22/2008
Publication #:	US20100074008	Pub Dt:	03/25/2010
Title:	SECTOR CONFIGURE REGISTERS FOR A FLASH DEVICE GENERATING MULTIPLE VIRTUAL GROUND DECODING SCHEMES

41

Patent #:	7881105	Issue Dt:	02/01/2011	Application #:	12234740	Filing Dt:	09/22/2008
Publication #:	US20100074009	Pub Dt:	03/25/2010
Title:	QUAD+BIT STORAGE IN TRAP BASED FLASH DESIGN USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL

42

Patent #:	7907448	Issue Dt:	03/15/2011	Application #:	12246981	Filing Dt:	10/07/2008
Publication #:	US20100085811	Pub Dt:	04/08/2010
Title:	SCALED DOWN SELECT GATES OF NAND FLASH MEMORY CELL STRINGS AND METHOD OF FORMING SAME

43

Patent #:	7848167	Issue Dt:	12/07/2010	Application #:	12255622	Filing Dt:	10/21/2008
Publication #:	US20100097876	Pub Dt:	04/22/2010
Title:	APPARATUS AND METHOD FOR GENERATING WIDE-RANGE REGULATED SUPPLY VOLTAGES FOR A FLASH MEMORY

44

Patent #:	8094509	Issue Dt:	01/10/2012	Application #:	12262123	Filing Dt:	10/30/2008
Publication #:	US20100110819	Pub Dt:	05/06/2010
Title:	APPARATUS AND METHOD FOR PLACEMENT OF BOOSTING CELL WITH ADAPTIVE BOOSTER SCHEME

45

Patent #:	8122181	Issue Dt:	02/21/2012	Application #:	12270616	Filing Dt:	11/13/2008
Publication #:	US20100122047	Pub Dt:	05/13/2010
Title:	SYSTEMS AND METHODS FOR ENHANCING A DATA STORE FOR HANDLING SEMANTIC INFORMATION

46

Patent #:	7849229	Issue Dt:	12/07/2010	Application #:	12277911	Filing Dt:	11/25/2008
Publication #:	US20100131676	Pub Dt:	05/27/2010
Title:	SPI ADDRESSING BEYOND 24-BITS

47

Patent #:	7985674	Issue Dt:	07/26/2011	Application #:	12290916	Filing Dt:	11/05/2008
Publication #:	US20100109067	Pub Dt:	05/06/2010
Title:	SIH4 SOAK FOR LOW HYDROGEN SIN DEPOSITION TO IMPROVE FLASH MEMORY DEVICE PERFORMANCE

48

Patent #:	8072802	Issue Dt:	12/06/2011	Application #:	12329475	Filing Dt:	12/05/2008
Publication #:	US20100142269	Pub Dt:	06/10/2010
Title:	MEMORY EMPLOYING REDUNDANT CELL ARRAY OF MULTI-BIT CELLS

49

Patent #:	7902520	Issue Dt:	03/08/2011	Application #:	12340288	Filing Dt:	12/19/2008
Publication #:	US20100155618	Pub Dt:	06/24/2010
Title:	RADIATION DETECTING ELECTRONIC DEVICE AND METHODS OF OPERATING

50

Patent #:	7935596	Issue Dt:	05/03/2011	Application #:	12342008	Filing Dt:	12/22/2008
Publication #:	US20100155816	Pub Dt:	06/24/2010
Title:	HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE

51

Patent #:	7943983	Issue Dt:	05/17/2011	Application #:	12342011	Filing Dt:	12/22/2008
Publication #:	US20100155785	Pub Dt:	06/24/2010
Title:	HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION

52

Patent #:	8040738	Issue Dt:	10/18/2011	Application #:	12346699	Filing Dt:	12/30/2008
Publication #:	US20110122708	Pub Dt:	05/26/2011
Title:	METHOD AND APPARATUS FOR PERFORMING SEMICONDUCTOR MEMORY OPERATIONS

53

Patent #:	7916529	Issue Dt:	03/29/2011	Application #:	12370932	Filing Dt:	02/13/2009
Publication #:	US20100208517	Pub Dt:	08/19/2010
Title:	PIN DIODE DEVICE AND ARCHITECTURE

54

Patent #:	8076199	Issue Dt:	12/13/2011	Application #:	12370950	Filing Dt:	02/13/2009
Publication #:	US20100207191	Pub Dt:	08/19/2010
Title:	METHOD AND DEVICE EMPLOYING POLYSILICON SCALING

55

Patent #:	8067314	Issue Dt:	11/29/2011	Application #:	12424023	Filing Dt:	04/15/2009
Publication #:	US20100264519	Pub Dt:	10/21/2010
Title:	GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPRAOCH TO TARGET CD FOR SELECTED TRANSISTORS

56

Patent #:	8085588	Issue Dt:	12/27/2011	Application #:	12433084	Filing Dt:	04/30/2009
Publication #:	US20100277987	Pub Dt:	11/04/2010
Title:	SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF

57

Patent #:	7840900	Issue Dt:	11/23/2010	Application #:	12433499	Filing Dt:	04/30/2009
Publication #:	US20100281293	Pub Dt:	11/04/2010
Title:	REPLACING RESET PIN IN BUSES WHILE GUARANTEEING SYSTEM RECOVERY

58

Patent #:	7940570	Issue Dt:	05/10/2011	Application #:	12494104	Filing Dt:	06/29/2009
Publication #:	US20100329024	Pub Dt:	12/30/2010
Title:	MEMORY EMPLOYING SEPARATE DYNAMIC REFERENCE AREAS

59

Patent #:	7961519	Issue Dt:	06/14/2011	Application #:	12494114	Filing Dt:	06/29/2009
Publication #:	US20100329003	Pub Dt:	12/30/2010
Title:	MEMORY EMPLOYING INDEPENDENT DYNAMIC REFERENCE AREAS

60

Patent #:	7978523	Issue Dt:	07/12/2011	Application #:	12512741	Filing Dt:	07/30/2009
Publication #:	US20090290425	Pub Dt:	11/26/2009
Title:	SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME

61

Patent #:	7969816	Issue Dt:	06/28/2011	Application #:	12548034	Filing Dt:	08/26/2009
Publication #:	US20110051529	Pub Dt:	03/03/2011
Title:	MEMORY DEVICE

62

Patent #:	8031528	Issue Dt:	10/04/2011	Application #:	12557721	Filing Dt:	09/11/2009
Publication #:	US20100027350	Pub Dt:	02/04/2010
Title:	FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT

63

Patent #:	7859096	Issue Dt:	12/28/2010	Application #:	12624117	Filing Dt:	11/23/2009
Publication #:	US20100102424	Pub Dt:	04/29/2010
Title:	SEMICONDUCTOR DEVICE

64

Patent #:	8134853	Issue Dt:	03/13/2012	Application #:	12642162	Filing Dt:	12/18/2009
Publication #:	US20110149630	Pub Dt:	06/23/2011
Title:	HIGH READ SPEED ELECTRONIC MEMORY WITH SERIAL ARRAY TRANSISTORS

65

Patent #:	7848154	Issue Dt:	12/07/2010	Application #:	12648984	Filing Dt:	12/29/2009
Publication #:	US20100135083	Pub Dt:	06/03/2010
Title:	NONVOLATILE MEMORY DEVICE

66

Patent #:	7986562	Issue Dt:	07/26/2011	Application #:	12650118	Filing Dt:	12/30/2009
Publication #:	US20100103732	Pub Dt:	04/29/2010
Title:	CONTROLLING AC DISTURBANCE WHILE PROGRAMMING

67

Patent #:	7972951	Issue Dt:	07/05/2011	Application #:	12688477	Filing Dt:	01/15/2010
Publication #:	US20100120239	Pub Dt:	05/13/2010
Title:	MEMORY DEVICE ETCH METHODS

68

Patent #:	7965574	Issue Dt:	06/21/2011	Application #:	12710153	Filing Dt:	02/22/2010
Publication #:	US20100149899	Pub Dt:	06/17/2010
Title:	TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS

69

Patent #:	8107294	Issue Dt:	01/31/2012	Application #:	12730452	Filing Dt:	03/24/2010
Publication #:	US20100177568	Pub Dt:	07/15/2010
Title:	READ MODE FOR FLASH MEMORY

70

Patent #:	7867848	Issue Dt:	01/11/2011	Application #:	12765646	Filing Dt:	04/22/2010
Publication #:	US20100203694	Pub Dt:	08/12/2010
Title:	METHODS FOR FABRICATING DUAL BIT FLASH MEMORY DEVICES

71

Patent #:	8035153	Issue Dt:	10/11/2011	Application #:	12788177	Filing Dt:	05/26/2010
Publication #:	US20100230743	Pub Dt:	09/16/2010
Title:	SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS

72

Patent #:	8045388	Issue Dt:	10/25/2011	Application #:	12819071	Filing Dt:	06/18/2010
Publication #:	US20100290291	Pub Dt:	11/18/2010
Title:	SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME

73

Patent #:	7906807	Issue Dt:	03/15/2011	Application #:	12827069	Filing Dt:	06/30/2010
Publication #:	US20100264480	Pub Dt:	10/21/2010
Title:	USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS

74

Patent #:	8144522	Issue Dt:	03/27/2012	Application #:	12831085	Filing Dt:	07/06/2010
Publication #:	US20100265775	Pub Dt:	10/21/2010
Title:	ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS

75

Patent #:	8148771	Issue Dt:	04/03/2012	Application #:	12837323	Filing Dt:	07/15/2010
Publication #:	US20100276801	Pub Dt:	11/04/2010
Title:	SEMICONDUCTOR DEVICE AND METHOD TO MANUFACTURE THEREOF

76

Patent #:	8076712	Issue Dt:	12/13/2011	Application #:	12840165	Filing Dt:	07/20/2010
Publication #:	US20100283100	Pub Dt:	11/11/2010
Title:	SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION

77

Patent #:	8114756	Issue Dt:	02/14/2012	Application #:	12850252	Filing Dt:	08/04/2010
Publication #:	US20120034755	Pub Dt:	02/09/2012
Title:	METHOD AND MANUFACTURE FOR HIGH VOLTAGE GATE OXIDE FORMATION AFTER SHALLOW TRENCH ISOLATION FORMATION

78

Patent #:	8203178	Issue Dt:	06/19/2012	Application #:	12860074	Filing Dt:	08/20/2010
Publication #:	US20100314753	Pub Dt:	12/16/2010
Title:	SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING

79

Patent #:	8031527	Issue Dt:	10/04/2011	Application #:	12871693	Filing Dt:	08/30/2010
Publication #:	US20100321996	Pub Dt:	12/23/2010
Title:	SEMICONDUCTOR DEVICE AND METHOD FOR ADJUSTING REFERENCE LEVELS OF REFERENCE CELLS

80

Patent #:	8094478	Issue Dt:	01/10/2012	Application #:	12878656	Filing Dt:	09/09/2010
Publication #:	US20110002177	Pub Dt:	01/06/2011
Title:	NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS

81

Patent #:	7972962	Issue Dt:	07/05/2011	Application #:	12887182	Filing Dt:	09/21/2010
Publication #:	US20110008966	Pub Dt:	01/13/2011
Title:	PLANARIZATION METHOD USING HYBRID OXIDE AND POLYSILICON CMP

82

Patent #:	8202779	Issue Dt:	06/19/2012	Application #:	12891310	Filing Dt:	09/27/2010
Publication #:	US20110233647	Pub Dt:	09/29/2011
Title:	METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER

83

Patent #:	7906395	Issue Dt:	03/15/2011	Application #:	12891481	Filing Dt:	09/27/2010
Publication #:	US20110012191	Pub Dt:	01/20/2011
Title:	SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS

84

Patent #:	7943980	Issue Dt:	05/17/2011	Application #:	12891532	Filing Dt:	09/27/2010
Publication #:	US20110013449	Pub Dt:	01/20/2011
Title:	SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS

85

Patent #:	7968464	Issue Dt:	06/28/2011	Application #:	12898551	Filing Dt:	10/05/2010
Publication #:	US20110027992	Pub Dt:	02/03/2011
Title:	MEMORY DEVICE WITH IMPROVED DATA RETENTION

86

Patent #:	8097518	Issue Dt:	01/17/2012	Application #:	12898968	Filing Dt:	10/06/2010
Publication #:	US20110020996	Pub Dt:	01/27/2011
Title:	SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

87

Patent #:	8023341	Issue Dt:	09/20/2011	Application #:	12903065	Filing Dt:	10/12/2010
Publication #:	US20110026287	Pub Dt:	02/03/2011
Title:	METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SEMICONDUCTOR DEVICE

88

Patent #:	8130584	Issue Dt:	03/06/2012	Application #:	12905716	Filing Dt:	10/15/2010
Publication #:	US20110032764	Pub Dt:	02/10/2011
Title:	SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME

89

Patent #:	8039891	Issue Dt:	10/18/2011	Application #:	12980716	Filing Dt:	12/29/2010
Publication #:	US20110095355	Pub Dt:	04/28/2011
Title:	SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS

90

Patent #:	8031537	Issue Dt:	10/04/2011	Application #:	12987466	Filing Dt:	01/10/2011
Publication #:	US20110103157	Pub Dt:	05/05/2011
Title:	TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY

Assignors

1

Exec Dt:

05/10/2010

2

Exec Dt:

05/10/2010

3

SPANSION TECHNOLOGY INC.

Exec Dt:

05/10/2010

4

SPANSION TECHNOLOGY LLC

Exec Dt:

05/10/2010

Assignee

1

BARCLAYS BANK PLC

745 SEVENTH AVENUE

NEW YORK, NEW YORK 10019

Correspondence name and address
	STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C
	1100 NEW YORK AVENUE, N.W.
	WASHINGTON, DC 20005

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