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Reel/Frame:029186/0755   Pages: 6
Recorded: 10/24/2012
Attorney Dkt #:VCI ABC 001
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 56
1
Patent #:
5675180
Issue Dt:
10/07/1997
Application #:
08265081
Filing Dt:
06/23/1994
Title:
VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS
2
Patent #:
5657206
Issue Dt:
08/12/1997
Application #:
08374421
Filing Dt:
01/19/1995
Title:
A CONDUCTIVE EXPOXY FLIP-CHIP PACKAGE AND METHOD
3
Patent #:
5698895
Issue Dt:
12/16/1997
Application #:
08376149
Filing Dt:
01/20/1995
Title:
SILICON SEGMENT PROGRAMMING METHOD AND APPARATUS
4
Patent #:
5661087
Issue Dt:
08/26/1997
Application #:
08476623
Filing Dt:
06/07/1995
Title:
VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS
5
Patent #:
6134118
Issue Dt:
10/17/2000
Application #:
08834798
Filing Dt:
04/03/1997
Title:
CONDUCTIVE EPOXY FLIP-CHIP PACKAGE AND METHOD
6
Patent #:
6188126
Issue Dt:
02/13/2001
Application #:
08842448
Filing Dt:
04/24/1997
Title:
VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS
7
Patent #:
5994170
Issue Dt:
11/30/1999
Application #:
08845654
Filing Dt:
04/25/1997
Title:
SILICON SEGMENT PROGRAMMING METHOD
8
Patent #:
5936302
Issue Dt:
08/10/1999
Application #:
08845655
Filing Dt:
04/25/1997
Title:
SPEAKER DIAPHRAGM
9
Patent #:
5837566
Issue Dt:
11/17/1998
Application #:
08847309
Filing Dt:
04/24/1997
Title:
VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS
10
Patent #:
6255726
Issue Dt:
07/03/2001
Application #:
08915620
Filing Dt:
08/21/1997
Title:
VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION
11
Patent #:
6098278
Issue Dt:
08/08/2000
Application #:
08917447
Filing Dt:
08/22/1997
Title:
METHOD FOR FORMING CONDUCTIVE EPOXY FLIP-CHIP ON CHIP
12
Patent #:
6271598
Issue Dt:
08/07/2001
Application #:
08918500
Filing Dt:
08/22/1997
Title:
CONDUCTIVE EPOXY FLIP-CHIP ON CHIP
13
Patent #:
6124633
Issue Dt:
09/26/2000
Application #:
08918501
Filing Dt:
08/22/1997
Title:
VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM
14
Patent #:
5891761
Issue Dt:
04/06/1999
Application #:
08918502
Filing Dt:
08/22/1997
Title:
METHOD FOR FORMING VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM
15
Patent #:
6080596
Issue Dt:
06/27/2000
Application #:
08920273
Filing Dt:
08/22/1997
Title:
METHOD FOR FORMING VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION
16
Patent #:
6177296
Issue Dt:
01/23/2001
Application #:
09273941
Filing Dt:
03/22/1999
Title:
METHOD FOR FORMING VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM
17
Patent #:
6486528
Issue Dt:
11/26/2002
Application #:
09378879
Filing Dt:
08/23/1999
Title:
SILICON SEGMENT PROGRAMMING APPARATUS AND THREE TERMINAL FUSE CONFIGURATION
18
Patent #:
7705432
Issue Dt:
04/27/2010
Application #:
11016558
Filing Dt:
12/17/2004
Publication #:
US20050224952
Pub Dt:
10/13/2005
Title:
THREE DIMENSIONAL SIX SURFACE CONFORMAL DIE COATING
19
Patent #:
7705432
Issue Dt:
04/27/2010
Application #:
11016558
Filing Dt:
12/17/2004
Publication #:
US20050224952
Pub Dt:
10/13/2005
Title:
THREE DIMENSIONAL SIX SURFACE CONFORMAL DIE COATING
20
Patent #:
7215018
Issue Dt:
05/08/2007
Application #:
11090969
Filing Dt:
03/25/2005
Publication #:
US20050230802
Pub Dt:
10/20/2005
Title:
STACKED DIE BGA OR LGA COMPONENT ASSEMBLY
21
Patent #:
7215018
Issue Dt:
05/08/2007
Application #:
11090969
Filing Dt:
03/25/2005
Publication #:
US20050230802
Pub Dt:
10/20/2005
Title:
STACKED DIE BGA OR LGA COMPONENT ASSEMBLY
22
Patent #:
7245021
Issue Dt:
07/17/2007
Application #:
11097829
Filing Dt:
03/31/2005
Publication #:
US20050258530
Pub Dt:
11/24/2005
Title:
MICROPEDE STACKED DIE COMPONENT ASSEMBLY
23
Patent #:
7245021
Issue Dt:
07/17/2007
Application #:
11097829
Filing Dt:
03/31/2005
Publication #:
US20050258530
Pub Dt:
11/24/2005
Title:
MICROPEDE STACKED DIE COMPONENT ASSEMBLY
24
Patent #:
8357999
Issue Dt:
01/22/2013
Application #:
11744142
Filing Dt:
05/03/2007
Publication #:
US20070284716
Pub Dt:
12/13/2007
Title:
ASSEMBLY HAVING STACKED DIE MOUNTED ON SUBSTRATE
25
Patent #:
7535109
Issue Dt:
05/19/2009
Application #:
11744153
Filing Dt:
05/03/2007
Publication #:
US20070252262
Pub Dt:
11/01/2007
Title:
DIE ASSEMBLY HAVING ELECTRICAL INTERCONNECT
26
Patent #:
7535109
Issue Dt:
05/19/2009
Application #:
11744153
Filing Dt:
05/03/2007
Publication #:
US20070252262
Pub Dt:
11/01/2007
Title:
DIE ASSEMBLY HAVING ELECTRICAL INTERCONNECT
27
Patent #:
NONE
Issue Dt:
Application #:
11849162
Filing Dt:
08/31/2007
Publication #:
US20070290377
Pub Dt:
12/20/2007
Title:
Three Dimensional Six Surface Conformal Die Coating
28
Patent #:
8742602
Issue Dt:
06/03/2014
Application #:
12046651
Filing Dt:
03/12/2008
Publication #:
US20080224279
Pub Dt:
09/18/2008
Title:
VERTICAL ELECTRICAL INTERCONNECT FORMED ON SUPPORT PRIOR TO DIE MOUNT
29
Patent #:
8723332
Issue Dt:
05/13/2014
Application #:
12124077
Filing Dt:
05/20/2008
Publication #:
US20080303131
Pub Dt:
12/11/2008
Title:
ELECTRICALLY INTERCONNECTED STACKED DIE ASSEMBLIES
30
Patent #:
NONE
Issue Dt:
Application #:
12124097
Filing Dt:
05/20/2008
Publication #:
US20090068790
Pub Dt:
03/12/2009
Title:
Electrical Interconnect Formed by Pulsed Dispense
31
Patent #:
7923349
Issue Dt:
04/12/2011
Application #:
12142589
Filing Dt:
06/19/2008
Publication #:
US20080315434
Pub Dt:
12/25/2008
Title:
WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS
32
Patent #:
7923349
Issue Dt:
04/12/2011
Application #:
12142589
Filing Dt:
06/19/2008
Publication #:
US20080315434
Pub Dt:
12/25/2008
Title:
WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS
33
Patent #:
NONE
Issue Dt:
Application #:
12143157
Filing Dt:
06/20/2008
Publication #:
US20080315407
Pub Dt:
12/25/2008
Title:
THREE-DIMENSIONAL CIRCUITRY FORMED ON INTEGRATED CIRCUIT DEVICE USING TWO-DIMENSIONAL FABRICATION
34
Patent #:
8704379
Issue Dt:
04/22/2014
Application #:
12199080
Filing Dt:
08/27/2008
Publication #:
US20090065916
Pub Dt:
03/12/2009
Title:
SEMICONDUCTOR DIE MOUNT BY CONFORMAL DIE COATING
35
Patent #:
7843046
Issue Dt:
11/30/2010
Application #:
12199667
Filing Dt:
08/27/2008
Publication #:
US20090206458
Pub Dt:
08/20/2009
Title:
FLAT LEADLESS PACKAGES AND STACKED LEADLESS PACKAGE ASSEMBLIES
36
Patent #:
7843046
Issue Dt:
11/30/2010
Application #:
12199667
Filing Dt:
08/27/2008
Publication #:
US20090206458
Pub Dt:
08/20/2009
Title:
FLAT LEADLESS PACKAGES AND STACKED LEADLESS PACKAGE ASSEMBLIES
37
Patent #:
NONE
Issue Dt:
Application #:
12251624
Filing Dt:
10/15/2008
Publication #:
US20090102038
Pub Dt:
04/23/2009
Title:
CHIP SCALE STACKED DIE PACKAGE
38
Patent #:
7863159
Issue Dt:
01/04/2011
Application #:
12323288
Filing Dt:
11/25/2008
Publication #:
US20090315174
Pub Dt:
12/24/2009
Title:
SEMICONDUCTOR DIE SEPARATION METHOD
39
Patent #:
7863159
Issue Dt:
01/04/2011
Application #:
12323288
Filing Dt:
11/25/2008
Publication #:
US20090315174
Pub Dt:
12/24/2009
Title:
SEMICONDUCTOR DIE SEPARATION METHOD
40
Patent #:
8181996
Issue Dt:
05/22/2012
Application #:
12368870
Filing Dt:
02/10/2009
Publication #:
US20100201120
Pub Dt:
08/12/2010
Title:
ROTATING UNION
41
Patent #:
8178978
Issue Dt:
05/15/2012
Application #:
12403175
Filing Dt:
03/12/2009
Publication #:
US20090230528
Pub Dt:
09/17/2009
Title:
SUPPORT MOUNTED ELECTRICALLY INTERCONNECTED DIE ASSEMBLY
42
Patent #:
7954980
Issue Dt:
06/07/2011
Application #:
12403575
Filing Dt:
03/13/2009
Publication #:
US20100232147
Pub Dt:
09/16/2010
Title:
FOLDING RECHARGEABLE WORKLIGHT
43
Patent #:
NONE
Issue Dt:
Application #:
12550012
Filing Dt:
08/28/2009
Publication #:
US20100052087
Pub Dt:
03/04/2010
Title:
Image Sensor
44
Patent #:
NONE
Issue Dt:
Application #:
12634598
Filing Dt:
12/09/2009
Publication #:
US20100140811
Pub Dt:
06/10/2010
Title:
SEMICONDUCTOR DIE INTERCONNECT FORMED BY AEROSOL APPLICATION OF ELECTRICALLY CONDUCTIVE MATERIAL
45
Patent #:
NONE
Issue Dt:
Application #:
12776262
Filing Dt:
05/07/2010
Publication #:
US20110115099
Pub Dt:
05/19/2011
Title:
Flip-chip underfill
46
Patent #:
8680687
Issue Dt:
03/25/2014
Application #:
12821454
Filing Dt:
06/23/2010
Publication #:
US20100327461
Pub Dt:
12/30/2010
Title:
ELECTRICAL INTERCONNECT FOR DIE STACKED IN ZIG-ZAG CONFIGURATION
47
Patent #:
8159053
Issue Dt:
04/17/2012
Application #:
12892739
Filing Dt:
09/28/2010
Publication #:
US20110012246
Pub Dt:
01/20/2011
Title:
FLAT LEADLESS PACKAGES AND STACKED LEADLESS PACKAGE ASSEMBLIES
48
Patent #:
8159053
Issue Dt:
04/17/2012
Application #:
12892739
Filing Dt:
09/28/2010
Publication #:
US20110012246
Pub Dt:
01/20/2011
Title:
FLAT LEADLESS PACKAGES AND STACKED LEADLESS PACKAGE ASSEMBLIES
49
Patent #:
9147583
Issue Dt:
09/29/2015
Application #:
12913529
Filing Dt:
10/27/2010
Publication #:
US20110266684
Pub Dt:
11/03/2011
Title:
Selective Die Electrical Insulation By Additive Process
50
Patent #:
8629543
Issue Dt:
01/14/2014
Application #:
12913604
Filing Dt:
10/27/2010
Publication #:
US20110037159
Pub Dt:
02/17/2011
Title:
ELECTRICALLY INTERCONNECTED STACKED DIE ASSEMBLIES
51
Patent #:
8912661
Issue Dt:
12/16/2014
Application #:
12939524
Filing Dt:
11/04/2010
Publication #:
US20110272825
Pub Dt:
11/10/2011
Title:
STACKED DIE ASSEMBLY HAVING REDUCED STRESS ELECTRICAL INTERCONNECTS
52
Patent #:
8884403
Issue Dt:
11/11/2014
Application #:
12982376
Filing Dt:
12/30/2010
Publication #:
US20110101505
Pub Dt:
05/05/2011
Title:
Semiconductor Die Array Structure
53
Patent #:
8324081
Issue Dt:
12/04/2012
Application #:
13041192
Filing Dt:
03/04/2011
Publication #:
US20110147943
Pub Dt:
06/23/2011
Title:
WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS
54
Patent #:
9153517
Issue Dt:
10/06/2015
Application #:
13109996
Filing Dt:
05/17/2011
Publication #:
US20120119385
Pub Dt:
05/17/2012
Title:
ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIES
55
Patent #:
8829677
Issue Dt:
09/09/2014
Application #:
13243877
Filing Dt:
09/23/2011
Publication #:
US20120248607
Pub Dt:
10/04/2012
Title:
SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS
56
Patent #:
9305862
Issue Dt:
04/05/2016
Application #:
13456126
Filing Dt:
04/25/2012
Publication #:
US20130099392
Pub Dt:
04/25/2013
Title:
SUPPORT MOUNTED ELECTRICALLY INTERCONNECTED DIE ASSEMBLY
Assignor
1
VERTICAL CIRCUITS, INC.
Exec Dt:
10/23/2012
Assignee
1
VERTICAL CIRCUITS (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
1100 LA AVENIDA STREET
BUILDING A
MOUNTAIN VIEW, CALIFORNIA 94043
Correspondence name and address
BILL KENNEDY
625 MIRAMONTES STREET
SUITE 201
HALF MOON BAY, CA 94019

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