|
Total properties:
11
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2003
|
Application #:
|
09423917
|
Filing Dt:
|
11/16/1999
|
|
Title:
|
PROCESSOR CONTROLLER FOR ACCELERATING INSTRUCTION ISSUING RATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
10432203
|
Filing Dt:
|
10/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
DATA ADDRESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10432307
|
Filing Dt:
|
04/16/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
|
Title:
|
CONTENT-ADDRESSABLE (ASSOCIATIVE) MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2011
|
Application #:
|
10432309
|
Filing Dt:
|
10/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/04/2004
| | | | |
|
Title:
|
BROADCASTING DATA ACROSS A BUS IN WHICH DATA TRANSMISSION CAN BE DELAYED IF A SNOOPING DEVICE IS NOT READY TO RECEIVE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
10499875
|
Filing Dt:
|
03/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
|
Title:
|
MEMORY ADDRESSING TECHNIQUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
10539493
|
Filing Dt:
|
01/17/2006
|
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
|
Title:
|
SCALABLE PROCESSING NETWORK FOR SEARCHING AND ADDING IN A CONTENT ADDRESSABLE MEMORY
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10591922
|
Filing Dt:
|
07/05/2007
|
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
|
Title:
|
Orthogonal Data Memory
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
11629293
|
Filing Dt:
|
11/09/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/06/2009
| | | | |
|
Title:
|
Improvements relating to data transfer apparatus
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
12993793
|
Filing Dt:
|
04/13/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2011
| | | | |
|
Title:
|
A PARALLEL PROCESSOR WITH SINGLE INSTRUCTION MULTIPLE DATA (SIMD) CONTROLLERS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12993801
|
Filing Dt:
|
04/13/2011
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2011
| | | | |
|
Title:
|
An Improved Parallel Processor Architecture for Improved Data Transfer
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13318404
|
Filing Dt:
|
11/01/2011
|
|
Publication #:
|
|
Pub Dt:
|
02/23/2012
| | | | |
|
Title:
|
CONTROLLING SIMD PARALLEL PROCESSORS
|
|
