|
Total properties:
97
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
07377168
|
Filing Dt:
|
07/10/1989
|
|
Title:
|
METHOD FOR READING NON-VOLATLILE FERROELECTRIC CAPACITOR MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
07443018
|
Filing Dt:
|
11/29/1989
|
|
Title:
|
NON-VOLATILE MEMORY CIRCUIT USING FERROELECTRIC CAPACITOR STORAGE ELEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/1994
|
Application #:
|
07977825
|
Filing Dt:
|
11/17/1992
|
|
Title:
|
NON-VOLATILE FERROELECTRIC MEMORY WITH FOLDED BIT LINES AND METHOD OF MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
08093790
|
Filing Dt:
|
07/19/1993
|
|
Title:
|
FERROELECTRID MEMORY DEVICE WITH CAPACITOR ELECTRODE IN DIRECT CONTACT WITH SOURCE REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/1995
|
Application #:
|
08212495
|
Filing Dt:
|
03/11/1994
|
|
Title:
|
PASSIVATION METHOD AND STRUCTURE FOR A FERROELECTRIC INTEGRATED CIRCUIT USING HARD CERAMIC MATERIALS OR THE LIKE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/1996
|
Application #:
|
08238802
|
Filing Dt:
|
05/06/1994
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A TRANSISTOR, A FERROELECTRIC CAPACITOR AND A HYDROGEN BARRIER FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/1995
|
Application #:
|
08303134
|
Filing Dt:
|
09/08/1994
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH A CONDUCTIVE REACTION-PREVENTING FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/1996
|
Application #:
|
08306686
|
Filing Dt:
|
09/16/1994
|
|
Title:
|
VOLTAGE REFERENCE FOR A FERROELECTRIC 1T/1C BASED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/1996
|
Application #:
|
08394467
|
Filing Dt:
|
02/27/1995
|
|
Title:
|
PASSIVATION METHOD AND STRUCTURE USING HARD CERAMIC MATERIALS OR THE LIKE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/1997
|
Application #:
|
08420293
|
Filing Dt:
|
04/10/1995
|
|
Title:
|
CIRCUIT AND METHOD FOR REDUCING A COMPENSATION OF A FERROELECTRIC CAPACITOR BY MULTIPLE PULSING OF THE PLATE LINE FOLLOWING A WRITE OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/1996
|
Application #:
|
08420752
|
Filing Dt:
|
04/12/1995
|
|
Title:
|
FERROELECTRIC MEMORY SENSING SCHEME USING BIT LINES PRECHARGED TO A LOGIC ONE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08468861
|
Filing Dt:
|
06/06/1995
|
|
Title:
|
LOW LOSS, REGULATED CHARGE PUMP WITH INTEGRATED FERROELECTRIC CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/1997
|
Application #:
|
08515558
|
Filing Dt:
|
08/16/1995
|
|
Title:
|
FERROELECTRIC NONVOLATILE RANDOM ACCESS MEMORY UTILIZING SELF-BOOTSTRAPPING PLATE LINE SEGMENT DRIVERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/1997
|
Application #:
|
08525497
|
Filing Dt:
|
09/08/1995
|
|
Title:
|
INTEGRATION OF HIGH VALUE CAPACITOR WITH FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/1999
|
Application #:
|
08544470
|
Filing Dt:
|
10/18/1995
|
|
Title:
|
METHOD OF MAKING INTEGRATION OF HIGH VALUE CAPACITOR WITH FERRO- ELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08616856
|
Filing Dt:
|
03/15/1996
|
|
Title:
|
USE OF CALCIUM AND STRONTIUM DOPANTS TO IMPROVE RETENTION PERFORMANCE IN A PZT FERROELECTRIC FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
08616913
|
Filing Dt:
|
03/15/1996
|
|
Title:
|
METHOD OF MEASURING RETENTION PERFORMANCE AND IMPRINT DEGRADATION OF FERROELECTRIC FILMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/1998
|
Application #:
|
08691132
|
Filing Dt:
|
08/01/1996
|
|
Title:
|
CIRCUIT AND METHOD FOR REDUCING COMPENSATION OF A FERROELECTRIC CAPACITOR BY MULTIPLE PULSING OF THE PLATE LINE FOLLOWING A WRITE OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1999
|
Application #:
|
08700076
|
Filing Dt:
|
08/20/1996
|
|
Title:
|
COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/1998
|
Application #:
|
08702363
|
Filing Dt:
|
08/23/1996
|
|
Title:
|
BANDGAP REFERENCE BASED POWER-ON DETECT CIRCUIT INCLUDING A SUPRESSION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/1998
|
Application #:
|
08723367
|
Filing Dt:
|
09/30/1996
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
08728740
|
Filing Dt:
|
10/11/1996
|
|
Title:
|
PARTIALLY OR COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
08828157
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
PARTIALLY OR COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08853527
|
Filing Dt:
|
05/09/1997
|
|
Title:
|
DUAL-LEVEL METALIZATION METHOD FOR INTEGRATED CIRCUIT FERROELECTRIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08861674
|
Filing Dt:
|
05/22/1997
|
|
Title:
|
USE OF CALCIUM AND STRONTIUM DOPANTS TO IMPROVE RETENTION PERFORMANCE IN A PZT FERROELECTRIC FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/1998
|
Application #:
|
08915054
|
Filing Dt:
|
08/20/1997
|
|
Title:
|
VOLTAGE BOOST CIRCUIT AND OPERATION THEREOF AT LOW POWER SUPPLY VOLTAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
08970448
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
PLATE LINE SEGMENTATION IN A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/1999
|
Application #:
|
08970452
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
REFERENCE CELL FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/1999
|
Application #:
|
08970453
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
SENSING METHODOLOGY FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/1999
|
Application #:
|
08970454
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
COLUMN DECODER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08970518
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
REFERENCE CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08970519
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
08970520
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
MEMORY CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08970522
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
PLATE LINE DRIVER CIRCUIT FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09021132
|
Filing Dt:
|
02/10/1998
|
|
Title:
|
INTEGRATED CIRCUIT MEMORY DEVICE INCORPORATING A NON-VOLATILE MEMORY ARRAY AND A RELATIVELY FASTER ACCESS TIME MEMORY CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09061362
|
Filing Dt:
|
04/15/1998
|
|
Title:
|
FERROELECTRIC THIN FILMS AND SOLUTIONS: COMPOSITIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09085280
|
Filing Dt:
|
05/27/1998
|
|
Title:
|
COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR USING A LEAD-ENHANCED ESCAPSULATION LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09164952
|
Filing Dt:
|
10/01/1998
|
|
Title:
|
HYDROGEN BARRIER ENCAPSULATION TECHNIQUES FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN CONJUNCTION WITH MULTILEVEL METAL PROCESSING FOR NON-VOLATILE INTEGRATED CIRCUIT MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09177392
|
Filing Dt:
|
10/23/1998
|
|
Title:
|
METHOD OF MANUFACTURING FERROELECTRIC MEMORY DEVICE USEFUL FOR PREVENTING HYDROGEN LINE DEGRADATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09283166
|
Filing Dt:
|
04/01/1999
|
|
Title:
|
BARRIER LAYER TO PROTECT A FERROELECTRIC CAPACITOR AFTER CONTACT HAS BEEN MADE TO THE CAPACITOR ELECTRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09351563
|
Filing Dt:
|
07/12/1999
|
|
Title:
|
FERROELECTRIC NON-VOLATILE LATCH CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09356534
|
Filing Dt:
|
07/19/1999
|
|
Title:
|
YIELD ENHANCEMENT TECHNIQUE FOR INTEGRATED CIRCUIT PROCESSING TO REDUCE EFFECTS OF UNDESIRED DIELECTRIC MOISTURE RETENTION AND SUBSEQUENT HYDROGEN OUT-DIFFUSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09427644
|
Filing Dt:
|
10/27/1999
|
|
Title:
|
MULTI-LAYER APPROACH FOR OPTIMIZING FERROELECTRIC FILM PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
|
09465724
|
Filing Dt:
|
12/17/1999
|
|
Title:
|
PLATE LINE DRIVER CIRCUIT FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
09505106
|
Filing Dt:
|
02/15/2000
|
|
Title:
|
METHOD OF FABRICATING PARTIALLY OR COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2004
|
Application #:
|
09556255
|
Filing Dt:
|
04/24/2000
|
|
Title:
|
HIGH TEMPERATURE DEPOSITION OF PT/TIOX FOR BOTTOM ELECTRODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
|
Application #:
|
09588153
|
Filing Dt:
|
06/05/2000
|
|
Title:
|
Ferroelectric memory device structure useful for preventing hydrogen line degradation
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09614157
|
Filing Dt:
|
07/11/2000
|
|
Title:
|
NONVOLATILE OCTAL LATCH AND D-TYPE REGISTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09641091
|
Filing Dt:
|
08/17/2000
|
|
Title:
|
METHOD OF MANUFACTURING FERROELECTRIC MEMORY DEVICE STRUCTURE USEFUL FOR PREVENTING HYDROGEN LINE DEGRADATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09663121
|
Filing Dt:
|
09/15/2000
|
|
Title:
|
Reference cell configuration for a 1T/1C ferroelectric memory
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09714879
|
Filing Dt:
|
11/16/2000
|
|
Title:
|
Ferroelectric voltage boost circuits
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09764223
|
Filing Dt:
|
01/16/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2001
| | | | |
|
Title:
|
SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2003
|
Application #:
|
09783496
|
Filing Dt:
|
02/13/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/09/2003
| | | | |
|
Title:
|
HYDROGEN BARRIER ENCAPSULATION TECHNIQUES FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN CONJUNCTION WITH MULTILEVEL METAL PROCESSING FOR NON-VOLATILE INTEGRATED CIRCUIT MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09797394
|
Filing Dt:
|
02/28/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/29/2002
| | | | |
|
Title:
|
STRUCTURE FOR MASKING INTEGRATED CAPACITORS OF PARTICULAR UTILITY FOR FERROELECTRIC MEMORY INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09816425
|
Filing Dt:
|
03/21/2001
|
|
Title:
|
METHOD FOR MANUFACTURING A FERROELECTRIC MEMORY CELL INCLUDING CO-ANNEALING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09864851
|
Filing Dt:
|
05/24/2001
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
TWO STAGE LOW VOLTAGE FERROELECTRIC BOOST CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09864858
|
Filing Dt:
|
05/24/2001
|
|
Title:
|
CMOS BOOSTING CIRCUIT UTILIZING FERROELECTRIC CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
09873772
|
Filing Dt:
|
06/04/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/03/2002
| | | | |
|
Title:
|
CAPACITIVELY COUPLED FERROELECTRIC RANDOM ACCESS MEMORY CELL AND A METHOD FOR MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09950560
|
Filing Dt:
|
09/10/2001
|
|
Title:
|
FERROELECTRIC RANDOM ACCESS MEMORY CONFIGURABLE OUTPUT DRIVER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
10022119
|
Filing Dt:
|
12/13/2001
|
|
Title:
|
SELF REFERENCING 1T/1C FERROELECTRIC RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
10076058
|
Filing Dt:
|
02/12/2002
|
|
Publication #:
|
|
Pub Dt:
|
08/22/2002
| | | | |
|
Title:
|
FERROELECTRIC NON-VOLATILE LOGIC ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
10114535
|
Filing Dt:
|
04/01/2002
|
|
Title:
|
FERROELECTRIC MEMORY WITH BIT-PLATE PARALLEL ARCHITECTURE AND OPERATING METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10190350
|
Filing Dt:
|
07/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2004
| | | | |
|
Title:
|
METHOD FOR PRODUCING CRYSTALLOGRAPHICALLY TEXTURED ELECTRODES FOR TEXTURED PZT CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
10190351
|
Filing Dt:
|
07/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2004
| | | | |
|
Title:
|
METHOD FOR PRODUCING CRYSTALLOGRAPHICALLY TEXTURED ELECTRODES FOR TEXTURED PZT CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
10233276
|
Filing Dt:
|
08/28/2002
|
|
Publication #:
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Pub Dt:
|
03/13/2003
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|
Title:
|
FERROELECTRIC RANDOM ACCESS MEMORY CONFIGURABLE OUTPUT DRIVER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10389276
|
Filing Dt:
|
03/13/2003
|
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Publication #:
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Pub Dt:
|
11/13/2003
| | | | |
|
Title:
|
COLUMN DECODER CONFIGURATION FOR A 1T/1C MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
10404941
|
Filing Dt:
|
03/31/2003
|
|
Title:
|
BIT-LINE SHIELDING METHOD FOR FERROELECTRIC MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10613427
|
Filing Dt:
|
07/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/20/2004
| | | | |
|
Title:
|
FERROELECTRIC NON-VOLATILE LOGIC ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10719108
|
Filing Dt:
|
11/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
IMPRINT-FREE CODING FOR FERROELECTRIC NONVOLATILE COUNTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10984065
|
Filing Dt:
|
11/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
|
Title:
|
CIRCUIT FOR GENERATING A CENTERED REFERENCE VOLTAGE FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
11021394
|
Filing Dt:
|
12/23/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
|
Title:
|
NON-VOLATILE COUNTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
11082526
|
Filing Dt:
|
03/17/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
|
Title:
|
COUNTING SCHEME WITH AUTOMATIC POINT-OF-REFERENCE GENERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
11426165
|
Filing Dt:
|
06/23/2006
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
CIRCUIT FOR GENERATING A CENTERED REFERENCE VOLTAGE FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11611053
|
Filing Dt:
|
12/14/2006
|
|
Publication #:
|
|
Pub Dt:
|
04/19/2007
| | | | |
|
Title:
|
IMPRINT-FREE CODING FOR FERROELECTRIC NONVOLATILE COUNTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2010
|
Application #:
|
11875922
|
Filing Dt:
|
10/21/2007
|
|
Publication #:
|
|
Pub Dt:
|
04/23/2009
| | | | |
|
Title:
|
2T/2C FERROELECTRIC RANDOM ACCESS MEMORY WITH COMPLEMENTARY BIT-LINE LOADS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2009
|
Application #:
|
11929326
|
Filing Dt:
|
10/30/2007
|
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
|
Title:
|
FAST POWER-ON DETECT CIRCUIT WITH ACCURATE TRIP-POINTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2011
|
Application #:
|
12415918
|
Filing Dt:
|
03/31/2009
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
|
Title:
|
METHOD FOR MITIGATING IMPRINT IN A FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
12833817
|
Filing Dt:
|
07/09/2010
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
|
Title:
|
LOW POWER, LOW PIN COUNT INTERFACE FOR AN RFID TRANSPONDER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
12833836
|
Filing Dt:
|
07/09/2010
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
|
Title:
|
FAST BLOCK WRITE USING AN INDIRECT MEMORY POINTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
12833845
|
Filing Dt:
|
07/09/2010
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
|
Title:
|
RFID ACCESS METHOD USING AN INDIRECT MEMORY POINTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
12833861
|
Filing Dt:
|
07/09/2010
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
|
Title:
|
INTERRUPT GENERATION AND ACKNOWLEDGMENT FOR RFID
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13355145
|
Filing Dt:
|
01/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
|
Title:
|
AUTHENTICATING FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) DEVICE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2018
|
Application #:
|
13467816
|
Filing Dt:
|
05/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
STACK PROCESSOR USING A FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) HAVING AN INSTRUCTION SET OPTIMIZED TO MINIMIZE MEMORY FETCH OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13467831
|
Filing Dt:
|
05/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
STACK PROCESSOR USING A FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) FOR BOTH CODE AND DATA SPACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13467849
|
Filing Dt:
|
05/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
STACK PROCESSOR USING A FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) FOR CODE SPACE AND A PORTION OF THE STACK MEMORY SPACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
13467874
|
Filing Dt:
|
05/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
|
Title:
|
STACK PROCESSOR USING A FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) FOR CODE SPACE AND A PORTION OF THE STACK MEMORY SPACE HAVING AN INSTRUCTION SET OPTIMIZED TO MINIMIZE PROCESSOR STACK ACCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
13470117
|
Filing Dt:
|
05/11/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/14/2013
| | | | |
|
Title:
|
ENHANCED HYDROGEN BARRIER ENCAPSULATION METHOD FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN AN F-RAM PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13490115
|
Filing Dt:
|
06/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/13/2012
| | | | |
|
Title:
|
POWER-ON SEQUENCING FOR AN RFID TAG
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13490163
|
Filing Dt:
|
06/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/13/2012
| | | | |
|
Title:
|
GENERATION OF VOLTAGE SUPPLY FOR LOW POWER DIGITAL CIRCUIT OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13490236
|
Filing Dt:
|
06/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/13/2012
| | | | |
|
Title:
|
BANDGAP READY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
13490254
|
Filing Dt:
|
06/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/13/2012
| | | | |
|
Title:
|
DYNAMIC POWER CLAMP FOR RFID POWER CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13490267
|
Filing Dt:
|
06/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
|
Title:
|
ANALOG DELAY CELLS FOR THE POWER SUPPLY OF AN RFID TAG
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13490285
|
Filing Dt:
|
06/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/13/2012
| | | | |
|
Title:
|
DYNAMIC ADJUSTING RFID DEMODULATION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13490296
|
Filing Dt:
|
06/06/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/13/2012
| | | | |
|
Title:
|
SHUNT REGULATOR CIRCUIT HAVING A SPLIT OUTPUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
13569735
|
Filing Dt:
|
08/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
|
Title:
|
METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) DEVICE STRUCTURE EMPLOYING REDUCED PROCESSING STEPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13569755
|
Filing Dt:
|
08/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
|
Title:
|
METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) WITH SIMULTANEOUS FORMATION OF SIDEWALL FERROELECTRIC CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13569785
|
Filing Dt:
|
08/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/14/2013
| | | | |
|
Title:
|
METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) HAVING A FERROELECTRIC CAPACITOR ALIGNED WITH A THREE DIMENSIONAL TRANSISTOR STRUCTURE
|
|
