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Reel/Frame:029499/0872   Pages: 4
Recorded: 12/19/2012
Attorney Dkt #:RA1109.P.US
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
13719724
Filing Dt:
12/19/2012
Publication #:
Pub Dt:
07/04/2013
Title:
Methods and Systems for Repairing Interior Device Layers in Three-Dimensional Integrated Circuits
Assignors
1
Exec Dt:
01/10/2012
2
Exec Dt:
01/04/2012
3
Exec Dt:
01/04/2012
4
Exec Dt:
01/09/2012
Assignee
1
1050 ENTERPRISE WAY
SUITE 700
SUNNYVALE, CALIFORNIA 94089
Correspondence name and address
SILICON EDGE LAW GROUP, LLP
6601 KOLL CENTER PARKWAY
SUITE 245
PLEASANTON, CA 94566

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