Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 029538/0262 | |
| Pages: | 19 |
| | Recorded: | 12/23/2012 | | |
| Attorney Dkt #: | 22524-01003 |
| Conveyance: | MERGER (SEE DOCUMENT FOR DETAILS). |
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Total properties:
3
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Patent #:
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Issue Dt:
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08/29/1995
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Application #:
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08040531
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Filing Dt:
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03/29/1993
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Title:
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TRANSISTOR-LEVEL TIMING AND POWER SIMULATOR AND POWER ANALYZER
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Patent #:
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Issue Dt:
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05/11/1999
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Application #:
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08468034
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Filing Dt:
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06/06/1995
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Title:
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A METHOD OF EXTRACTING LAYOUT PARASITICS FOR NETS OF AN INTEGRATED CIRCUIT USING A CONNECTIVITY-BASED APPROACH
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Patent #:
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Issue Dt:
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09/03/1996
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Application #:
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08500304
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Filing Dt:
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07/10/1995
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Title:
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TRANSISTOR-LEVEL TIMING AND SIMULATOR AND POWER ANALYZER
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Assignee
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| 700 EAST MIDDLEFIELD ROAD |
| MOUNTAIN VIEW, CA 94043, CALIFORNIA 94043 |
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Correspondence name and address
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RAJIV P. PATEL
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FENWICK & WEST LLP
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801 CALIFORNIA STREET
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MOUNTAIN VIEW, CA 94041
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