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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:029625/0763   Pages: 6
Recorded: 01/14/2013
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 65
1
Patent #:
8268086
Issue Dt:
09/18/2012
Application #:
10927821
Filing Dt:
08/27/2004
Publication #:
US20050274397
Pub Dt:
12/15/2005
Title:
METHOD FOR PROCESSING A PHOTOMASK FOR SEMICONDUCTOR DEVICES
2
Patent #:
8309456
Issue Dt:
11/13/2012
Application #:
11249141
Filing Dt:
10/11/2005
Publication #:
US20060110902
Pub Dt:
05/25/2006
Title:
METHOD AND SYSTEM FOR METAL BARRIER AND SEED INTEGRATION
3
Patent #:
8614487
Issue Dt:
12/24/2013
Application #:
11377936
Filing Dt:
03/15/2006
Publication #:
US20070181917
Pub Dt:
08/09/2007
Title:
SPLIT DUAL GATE FIELD EFFECT TRANSISTOR
4
Patent #:
8686507
Issue Dt:
04/01/2014
Application #:
11517546
Filing Dt:
09/06/2006
Publication #:
US20070164362
Pub Dt:
07/19/2007
Title:
SYSTEM AND METHOD FOR I/O ESD PROTECTION WITH FLOATING AND/OR BIASED POLYSILICON REGIONS
5
Patent #:
8420550
Issue Dt:
04/16/2013
Application #:
11611403
Filing Dt:
12/15/2006
Publication #:
US20080142052
Pub Dt:
06/19/2008
Title:
METHOD FOR CLEANING BACKSIDE ETCH DURING MANUFACTURE OF INTEGRATED CIRCUITS
6
Patent #:
8304821
Issue Dt:
11/06/2012
Application #:
11615969
Filing Dt:
12/23/2006
Publication #:
US20070181922
Pub Dt:
08/09/2007
Title:
CMOS IMAGE SENSOR
7
Patent #:
7534711
Issue Dt:
05/19/2009
Application #:
11615972
Filing Dt:
12/23/2006
Publication #:
US20080146030
Pub Dt:
06/19/2008
Title:
SYSTEM AND METHOD FOR DIRECT ETCHING
8
Patent #:
8323990
Issue Dt:
12/04/2012
Application #:
11728184
Filing Dt:
03/22/2007
Publication #:
US20080128693
Pub Dt:
06/05/2008
Title:
RELIABILITY TEST STRUCTURE FOR MULTILEVEL INTERCONNECT
9
Patent #:
8828867
Issue Dt:
09/09/2014
Application #:
11950370
Filing Dt:
12/04/2007
Publication #:
US20080138981
Pub Dt:
06/12/2008
Title:
SYSTEM AND METHOD FOR MANUFACTURING CONTACT
10
Patent #:
8749006
Issue Dt:
06/10/2014
Application #:
11952901
Filing Dt:
12/07/2007
Publication #:
US20080135897
Pub Dt:
06/12/2008
Title:
METHOD AND SYSTEM FOR IMAGE SENSOR AND LENS ON A SILICON BACK PLANE WAFER
11
Patent #:
8242017
Issue Dt:
08/14/2012
Application #:
12044254
Filing Dt:
03/07/2008
Publication #:
US20090227103
Pub Dt:
09/10/2009
Title:
METHOD AND STRUCTURE FOR COPPER GAP FILL PLATING OF INTERCONNECT STRUCTURES FOR SEMICONDUCTOR INTEGRATED CIRCUITS
12
Patent #:
8551831
Issue Dt:
10/08/2013
Application #:
12234393
Filing Dt:
09/19/2008
Publication #:
US20090152599
Pub Dt:
06/18/2009
Title:
SILICON GERMANIUM AND POLYSILICON GATE STRUCTURE FOR STRAINED SILICON TRANSISTORS
13
Patent #:
8187950
Issue Dt:
05/29/2012
Application #:
12258366
Filing Dt:
10/24/2008
Publication #:
US20100006975
Pub Dt:
01/14/2010
Title:
METHOD OF ELIMINATING MICRO-TRENCHES DURING SPACER ETCH
14
Patent #:
8318571
Issue Dt:
11/27/2012
Application #:
12258375
Filing Dt:
10/24/2008
Publication #:
US20100003799
Pub Dt:
01/07/2010
Title:
METHOD FOR FORMING P-TYPE LIGHTLY DOPED DRAIN REGION USING GERMANIUM PRE-AMORPHOUS TREATMENT
15
Patent #:
8415218
Issue Dt:
04/09/2013
Application #:
12259128
Filing Dt:
10/27/2008
Publication #:
US20100001334
Pub Dt:
01/07/2010
Title:
ATOMIC LAYER DEPOSITION EPITAXIAL SILICON GROWTH FOR TFT FLASH MEMORY CELL
16
Patent #:
8513079
Issue Dt:
08/20/2013
Application #:
12259144
Filing Dt:
10/27/2008
Publication #:
US20100001281
Pub Dt:
01/07/2010
Title:
TFT SAS MEMORY CELL STRUCTURES
17
Patent #:
8420466
Issue Dt:
04/16/2013
Application #:
12259165
Filing Dt:
10/27/2008
Publication #:
US20100001282
Pub Dt:
01/07/2010
Title:
A METHOD OF FORMING TFT FLOATING GATE MEMORY CELL STRUCTURES
18
Patent #:
8247258
Issue Dt:
08/21/2012
Application #:
12259172
Filing Dt:
10/27/2008
Publication #:
US20100197066
Pub Dt:
08/05/2010
Title:
METHOD OF INTERCONNECT FOR IMAGE SENSOR
19
Patent #:
8804100
Issue Dt:
08/12/2014
Application #:
12398143
Filing Dt:
03/04/2009
Publication #:
US20100316958
Pub Dt:
12/16/2010
Title:
METHOD AND SYSTEM FOR CALIBRATING EXPOSURE SYSTEM FOR MANUFACTURING OF INTEGRATED CIRCUITS
20
Patent #:
9310643
Issue Dt:
04/12/2016
Application #:
12420706
Filing Dt:
04/08/2009
Publication #:
US20090200564
Pub Dt:
08/13/2009
Title:
Method and Structure for Fabricating Smooth Mirrors for Liquid Crystal on Silicon Devices
21
Patent #:
8143666
Issue Dt:
03/27/2012
Application #:
12576231
Filing Dt:
10/08/2009
Publication #:
US20100025686
Pub Dt:
02/04/2010
Title:
SEMICONDUCTOR DEVICE WITH AMORPHOUS SILICON MONOS MEMORY CELL STRUCTURE AND METHOD FOR MANUFACTURING THEREOF
22
Patent #:
8373272
Issue Dt:
02/12/2013
Application #:
12582690
Filing Dt:
10/20/2009
Publication #:
US20110037177
Pub Dt:
02/17/2011
Title:
DEVICE UNDER BONDING PAD USING SINGLE METALLIZATION
23
Patent #:
NONE
Issue Dt:
Application #:
12582694
Filing Dt:
10/20/2009
Publication #:
US20100165165
Pub Dt:
07/01/2010
Title:
METHOD AND DEVICE FOR A CMOS IMAGE SENSOR
24
Patent #:
8415663
Issue Dt:
04/09/2013
Application #:
12616749
Filing Dt:
11/11/2009
Publication #:
US20100164508
Pub Dt:
07/01/2010
Title:
SYSTEM AND METHOD FOR TEST STRUCTURE ON A WAFER
25
Patent #:
8283726
Issue Dt:
10/09/2012
Application #:
12623363
Filing Dt:
11/20/2009
Publication #:
US20100059824
Pub Dt:
03/11/2010
Title:
SYSTEM AND METHOD FOR I/O ESD PROTECTION WITH POLYSILICON REGIONS FABRICATED BY PROCESSES FOR MAKING CORE TRANSISTORS
26
Patent #:
8679864
Issue Dt:
03/25/2014
Application #:
12637688
Filing Dt:
12/14/2009
Publication #:
US20100167428
Pub Dt:
07/01/2010
Title:
METHOD AND SYSTEM FOR DETERMINING SEMICONDUCTOR CHARACTERISTICS
27
Patent #:
8105898
Issue Dt:
01/31/2012
Application #:
12647362
Filing Dt:
12/24/2009
Publication #:
US20100227464
Pub Dt:
09/09/2010
Title:
METHOD AND STRUCTURE FOR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS
28
Patent #:
8762902
Issue Dt:
06/24/2014
Application #:
12649278
Filing Dt:
12/29/2009
Publication #:
US20100169852
Pub Dt:
07/01/2010
Title:
SYSTEM AND METHOD FOR DETECTING ONE OR MORE WINDING PATHS FOR PATTERNS ON A RETICLE FOR THE MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUITS
29
Patent #:
8217471
Issue Dt:
07/10/2012
Application #:
12650494
Filing Dt:
12/30/2009
Publication #:
US20100171186
Pub Dt:
07/08/2010
Title:
SYSTEM AND METHOD FOR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR
30
Patent #:
8446983
Issue Dt:
05/21/2013
Application #:
12692603
Filing Dt:
01/23/2010
Publication #:
US20100189196
Pub Dt:
07/29/2010
Title:
AMPLITUDE SHIFT KEYED (ASK) DEMODULATION PATTERN AND USE IN RADIO FREQUENCY IDENTIFICATION (RFID)
31
Patent #:
8748260
Issue Dt:
06/10/2014
Application #:
12704495
Filing Dt:
02/11/2010
Publication #:
US20110045661
Pub Dt:
02/24/2011
Title:
METHOD FOR MANUFACTURING NANO-CRYSTALLINE SILICON MATERIAL FOR SEMICONDUCTOR INTEGRATED CIRCUITS
32
Patent #:
8114732
Issue Dt:
02/14/2012
Application #:
12704502
Filing Dt:
02/11/2010
Publication #:
US20110045649
Pub Dt:
02/24/2011
Title:
METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH AL2O3/NANO-CRYSTALLINE SI LAYER
33
Patent #:
8318556
Issue Dt:
11/27/2012
Application #:
12704511
Filing Dt:
02/11/2010
Publication #:
US20110042732
Pub Dt:
02/24/2011
Title:
METHOD AND SYSTEM FOR CONTINUOUS LINE-TYPE LANDING POLYSILICON CONTACT (LPC) STRUCTURES
34
Patent #:
8319959
Issue Dt:
11/27/2012
Application #:
12724276
Filing Dt:
03/15/2010
Publication #:
US20100233594
Pub Dt:
09/16/2010
Title:
SYSTEM AND METHOD FOR QUALITY ASSURANCE FOR RETICLES USED IN MANUFACTURING OF INTEGRATED CIRCUITS
35
Patent #:
8320193
Issue Dt:
11/27/2012
Application #:
12794697
Filing Dt:
06/04/2010
Publication #:
US20110063924
Pub Dt:
03/17/2011
Title:
METHOD OF FLASH MEMORY DESIGN WITH DIFFERENTIAL CELL FOR BETTER ENDURANCE
36
Patent #:
8295096
Issue Dt:
10/23/2012
Application #:
12794698
Filing Dt:
06/04/2010
Publication #:
US20110051522
Pub Dt:
03/03/2011
Title:
METHOD OF PROGRAMMING FLASH MEMORY OF THE DIFFERENTIAL CELL STRUCTURES FOR BETTER ENDURANCE
37
Patent #:
8354707
Issue Dt:
01/15/2013
Application #:
12833939
Filing Dt:
07/09/2010
Publication #:
US20100276745
Pub Dt:
11/04/2010
Title:
ELECTRICALLY PROGRAMMABLE DEVICE WITH EMBEDDED EEPROM AND METHOD FOR MAKING THEREOF
38
Patent #:
8269311
Issue Dt:
09/18/2012
Application #:
12845651
Filing Dt:
07/28/2010
Publication #:
US20110062551
Pub Dt:
03/17/2011
Title:
MULTILAYER OXIDE ON NITRIDE ON OXIDE STRUCTURE AND METHOD FOR THE MANUFACTURE OF SEMICONDUCTOR DEVICES
39
Patent #:
8507378
Issue Dt:
08/13/2013
Application #:
12848068
Filing Dt:
07/30/2010
Publication #:
US20110037130
Pub Dt:
02/17/2011
Title:
METHOD AND STRUCTURE FOR SELF ALIGNED CONTACT FOR INTEGRATED CIRCUITS
40
Patent #:
9269625
Issue Dt:
02/23/2016
Application #:
12848229
Filing Dt:
08/02/2010
Publication #:
US20110187909
Pub Dt:
08/04/2011
Title:
METHOD AND SYSTEM FOR CMOS IMAGE SENSING DEVICE
41
Patent #:
8521956
Issue Dt:
08/27/2013
Application #:
12857513
Filing Dt:
08/16/2010
Publication #:
US20110066777
Pub Dt:
03/17/2011
Title:
WIRELESS MEMORY CARD AND METHOD THEREOF
42
Patent #:
8309472
Issue Dt:
11/13/2012
Application #:
12869620
Filing Dt:
08/26/2010
Publication #:
US20110065281
Pub Dt:
03/17/2011
Title:
METHOD OF RAPID THERMAL TREATMENT USING HIGH ENERGY ELECTROMAGNETIC RADIATION OF A SEMICONDUCTOR SUBSTRATE FOR FORMATION OF EPITAXIAL MATERIALS
43
Patent #:
8685826
Issue Dt:
04/01/2014
Application #:
12884057
Filing Dt:
09/16/2010
Publication #:
US20110070711
Pub Dt:
03/24/2011
Title:
METHOD FOR MANUFACTURING NANO-CRYSTALLINE SILICON MATERIAL FROM CHLORIDE CHEMISTRIES FOR THE SEMICONDUCTOR INTEGRATED CIRCUITS
44
Patent #:
8329529
Issue Dt:
12/11/2012
Application #:
12885248
Filing Dt:
09/17/2010
Publication #:
US20110074036
Pub Dt:
03/31/2011
Title:
VIA CONTACT STRUCTURES AND METHODS FOR INTEGRATED CIRCUITS
45
Patent #:
8815680
Issue Dt:
08/26/2014
Application #:
12886534
Filing Dt:
09/20/2010
Publication #:
US20110084328
Pub Dt:
04/14/2011
Title:
NON-VOLATILE MEMORY HAVING NANO CRYSTALLINE SILICON HILLOCKS FLOATING GATE
46
Patent #:
NONE
Issue Dt:
Application #:
12887481
Filing Dt:
09/21/2010
Publication #:
US20110095396
Pub Dt:
04/28/2011
Title:
METHOD AND STRUCTURE FOR SILICON NANOCRYSTAL CAPACITOR DEVICES FOR INTEGRATED CIRCUITS
47
Patent #:
NONE
Issue Dt:
Application #:
12887491
Filing Dt:
09/21/2010
Publication #:
US20110074459
Pub Dt:
03/31/2011
Title:
STRUCTURE AND METHOD FOR SEMICONDUCTOR TESTING
48
Patent #:
8119479
Issue Dt:
02/21/2012
Application #:
12887496
Filing Dt:
09/21/2010
Publication #:
US20110089479
Pub Dt:
04/21/2011
Title:
SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE AND METHOD OF MANUFACTURE
49
Patent #:
8513727
Issue Dt:
08/20/2013
Application #:
12892879
Filing Dt:
09/28/2010
Publication #:
US20110163369
Pub Dt:
07/07/2011
Title:
SURROUNDING STACKED GATE MULTI-GATE FET STRUCTURE NONVOLATILE MEMORY DEVICE
50
Patent #:
8513721
Issue Dt:
08/20/2013
Application #:
12902134
Filing Dt:
10/11/2010
Publication #:
US20120181589
Pub Dt:
07/19/2012
Title:
CMOS IMAGE SENSOR WITH NON-CONTACT STRUCTURE
51
Patent #:
8354704
Issue Dt:
01/15/2013
Application #:
12917419
Filing Dt:
11/01/2010
Publication #:
US20110115012
Pub Dt:
05/19/2011
Title:
METHOD FOR FABRICATING AN ENLARGED OXIDE-NITRIDE-OXIDE STRUCTURE FOR NAND FLASH MEMORY SEMICONDUCTOR DEVICES
52
Patent #:
8815615
Issue Dt:
08/26/2014
Application #:
12938158
Filing Dt:
11/02/2010
Publication #:
US20120070915
Pub Dt:
03/22/2012
Title:
METHOD FOR COPPER HILLOCK REDUCTION
53
Patent #:
NONE
Issue Dt:
Application #:
12938166
Filing Dt:
11/02/2010
Publication #:
US20110109856
Pub Dt:
05/12/2011
Title:
METHOD AND STRUCTURE FOR ELECTRO-PLATING ALUMINUM SPECIES FOR TOP METAL FORMATION OF LIQUID CRYSTAL ON SILICON DISPLAYS
54
Patent #:
NONE
Issue Dt:
Application #:
12938178
Filing Dt:
11/02/2010
Publication #:
US20110108889
Pub Dt:
05/12/2011
Title:
SEMICONDUCTOR DEVICE WITH A 7F2 CELL STRUCTURE
55
Patent #:
8383444
Issue Dt:
02/26/2013
Application #:
12953410
Filing Dt:
11/23/2010
Publication #:
US20110149085
Pub Dt:
06/23/2011
Title:
METHOD FOR DETERMINING COLOR USING CMOS IMAGE SENSOR
56
Patent #:
8404510
Issue Dt:
03/26/2013
Application #:
12953414
Filing Dt:
11/23/2010
Publication #:
US20110070677
Pub Dt:
03/24/2011
Title:
METHOD FOR FORMING A CMOS IMAGE SENSING PIXEL
57
Patent #:
8470669
Issue Dt:
06/25/2013
Application #:
12959229
Filing Dt:
12/02/2010
Publication #:
US20110133264
Pub Dt:
06/09/2011
Title:
SYSTEM AND METHOD FOR EEPROM ARCHITECTURE
58
Patent #:
8546224
Issue Dt:
10/01/2013
Application #:
12965808
Filing Dt:
12/10/2010
Publication #:
US20110140190
Pub Dt:
06/16/2011
Title:
METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH ALUMINUM OXIDE LAYER
59
Patent #:
9064804
Issue Dt:
06/23/2015
Application #:
12968264
Filing Dt:
12/14/2010
Publication #:
US20110140191
Pub Dt:
06/16/2011
Title:
METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH SILICON NITRIDE LAYER
60
Patent #:
NONE
Issue Dt:
Application #:
12969563
Filing Dt:
12/15/2010
Publication #:
US20110140192
Pub Dt:
06/16/2011
Title:
METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH FLOATING POLYSILICON LAYER
61
Patent #:
NONE
Issue Dt:
Application #:
12978346
Filing Dt:
12/23/2010
Publication #:
US20110156123
Pub Dt:
06/30/2011
Title:
METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH HAFNIUM OXIDE LAYER
62
Patent #:
8598001
Issue Dt:
12/03/2013
Application #:
12978473
Filing Dt:
12/24/2010
Publication #:
US20110156129
Pub Dt:
06/30/2011
Title:
METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH HAFNIUM OXIDE AND NANO-CRYSTALLINE SILICON LAYER
63
Patent #:
8383445
Issue Dt:
02/26/2013
Application #:
12979258
Filing Dt:
12/27/2010
Publication #:
US20110204425
Pub Dt:
08/25/2011
Title:
METHOD AND DEVICE FOR CMOS IMAGE SENSING WITH MULTIPLE GATE OXIDE THICKNESSES
64
Patent #:
8350356
Issue Dt:
01/08/2013
Application #:
12979265
Filing Dt:
12/27/2010
Publication #:
US20120061765
Pub Dt:
03/15/2012
Title:
ANTI-FUSE BASED PROGRAMMABLE SERIAL NUMBER GENERATOR
65
Patent #:
8319286
Issue Dt:
11/27/2012
Application #:
12979306
Filing Dt:
12/27/2010
Publication #:
US20120001261
Pub Dt:
01/05/2012
Title:
SYSTEM AND METHOD FOR INPUT PIN ESD PROTECTION WITH FLOATING AND/OR BIASED POLYSILICON REGIONS
Assignor
1
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Exec Dt:
11/23/2012
Assignees
1
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
18 ZHANG JIANG RD.
PUDONG NEW AREA
SHANGHAI, CHINA 201203
2
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
18 WEN CHANG ROAD, ECONOMIC-TECHNOLOGICAL DEVELOPMENT AREA
DAXING DISTRICT
BEIJING, CHINA 100176
Correspondence name and address
KILPATRICK TOWNSEND AND STOCKTOWN, LLP
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO, CA 94111-3834

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