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Patent Assignment Details

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Reel/Frame:	029683/0797			Pages:	10
		Recorded:	01/23/2013
Attorney Dkt #:	TIPI 5.2-236
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 33

Patent #:	4658146	Issue Dt:	04/14/1987	Application #:	06709267	Filing Dt:	03/07/1985
Title:	EXTENDED CAVITY LASER READOUT APPARATUS

Patent #:	4707814	Issue Dt:	11/17/1987	Application #:	06711842	Filing Dt:	03/14/1985
Title:	EXTENDED CAVITY LASER RECORDING METHOD AND APPARATUS

Patent #:	4897708	Issue Dt:	01/30/1990	Application #:	06887129	Filing Dt:	07/17/1986
Title:	SEMICONDUCTOR WAFER ARRAY

Patent #:	4954875	Issue Dt:	09/04/1990	Application #:	07114633	Filing Dt:	10/28/1987
Title:	SEMICONDUCTOR WAFER ARRAY WITH ELECTRICALLY CONDUCTIVE COMPLIANT MATERIAL

Patent #:	5675180	Issue Dt:	10/07/1997	Application #:	08265081	Filing Dt:	06/23/1994
Title:	VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS

Patent #:	5657206	Issue Dt:	08/12/1997	Application #:	08374421	Filing Dt:	01/19/1995
Title:	A CONDUCTIVE EXPOXY FLIP-CHIP PACKAGE AND METHOD

Patent #:	5698895	Issue Dt:	12/16/1997	Application #:	08376149	Filing Dt:	01/20/1995
Title:	SILICON SEGMENT PROGRAMMING METHOD AND APPARATUS

Patent #:	5661087	Issue Dt:	08/26/1997	Application #:	08476623	Filing Dt:	06/07/1995
Title:	VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS

Patent #:	6134118	Issue Dt:	10/17/2000	Application #:	08834798	Filing Dt:	04/03/1997
Title:	CONDUCTIVE EPOXY FLIP-CHIP PACKAGE AND METHOD

Patent #:	6188126	Issue Dt:	02/13/2001	Application #:	08842448	Filing Dt:	04/24/1997
Title:	VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS

Patent #:	5994170	Issue Dt:	11/30/1999	Application #:	08845654	Filing Dt:	04/25/1997
Title:	SILICON SEGMENT PROGRAMMING METHOD

Patent #:	5936302	Issue Dt:	08/10/1999	Application #:	08845655	Filing Dt:	04/25/1997
Title:	SPEAKER DIAPHRAGM

Patent #:	5837566	Issue Dt:	11/17/1998	Application #:	08847309	Filing Dt:	04/24/1997
Title:	VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS

Patent #:	6255726	Issue Dt:	07/03/2001	Application #:	08915620	Filing Dt:	08/21/1997
Title:	VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION

Patent #:	6098278	Issue Dt:	08/08/2000	Application #:	08917447	Filing Dt:	08/22/1997
Title:	METHOD FOR FORMING CONDUCTIVE EPOXY FLIP-CHIP ON CHIP

Patent #:	6271598	Issue Dt:	08/07/2001	Application #:	08918500	Filing Dt:	08/22/1997
Title:	CONDUCTIVE EPOXY FLIP-CHIP ON CHIP

Patent #:	6124633	Issue Dt:	09/26/2000	Application #:	08918501	Filing Dt:	08/22/1997
Title:	VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM

Patent #:	5891761	Issue Dt:	04/06/1999	Application #:	08918502	Filing Dt:	08/22/1997
Title:	METHOD FOR FORMING VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM

Patent #:	6080596	Issue Dt:	06/27/2000	Application #:	08920273	Filing Dt:	08/22/1997
Title:	METHOD FOR FORMING VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION

Patent #:	6177296	Issue Dt:	01/23/2001	Application #:	09273941	Filing Dt:	03/22/1999
Title:	METHOD FOR FORMING VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM

Patent #:	6486528	Issue Dt:	11/26/2002	Application #:	09378879	Filing Dt:	08/23/1999
Title:	SILICON SEGMENT PROGRAMMING APPARATUS AND THREE TERMINAL FUSE CONFIGURATION

Patent #:	7705432	Issue Dt:	04/27/2010	Application #:	11016558	Filing Dt:	12/17/2004
Publication #:	US20050224952	Pub Dt:	10/13/2005
Title:	THREE DIMENSIONAL SIX SURFACE CONFORMAL DIE COATING

Patent #:	7215018	Issue Dt:	05/08/2007	Application #:	11090969	Filing Dt:	03/25/2005
Publication #:	US20050230802	Pub Dt:	10/20/2005
Title:	STACKED DIE BGA OR LGA COMPONENT ASSEMBLY

Patent #:	7245021	Issue Dt:	07/17/2007	Application #:	11097829	Filing Dt:	03/31/2005
Publication #:	US20050258530	Pub Dt:	11/24/2005
Title:	MICROPEDE STACKED DIE COMPONENT ASSEMBLY

Patent #:	8357999	Issue Dt:	01/22/2013	Application #:	11744142	Filing Dt:	05/03/2007
Publication #:	US20070284716	Pub Dt:	12/13/2007
Title:	ASSEMBLY HAVING STACKED DIE MOUNTED ON SUBSTRATE

Patent #:	7535109	Issue Dt:	05/19/2009	Application #:	11744153	Filing Dt:	05/03/2007
Publication #:	US20070252262	Pub Dt:	11/01/2007
Title:	DIE ASSEMBLY HAVING ELECTRICAL INTERCONNECT

Patent #:	NONE	Issue Dt:		Application #:	11849162	Filing Dt:	08/31/2007
Publication #:	US20070290377	Pub Dt:	12/20/2007
Title:	Three Dimensional Six Surface Conformal Die Coating

Patent #:	8742602	Issue Dt:	06/03/2014	Application #:	12046651	Filing Dt:	03/12/2008
Publication #:	US20080224279	Pub Dt:	09/18/2008
Title:	VERTICAL ELECTRICAL INTERCONNECT FORMED ON SUPPORT PRIOR TO DIE MOUNT

Patent #:	8723332	Issue Dt:	05/13/2014	Application #:	12124077	Filing Dt:	05/20/2008
Publication #:	US20080303131	Pub Dt:	12/11/2008
Title:	ELECTRICALLY INTERCONNECTED STACKED DIE ASSEMBLIES

Patent #:	7923349	Issue Dt:	04/12/2011	Application #:	12142589	Filing Dt:	06/19/2008
Publication #:	US20080315434	Pub Dt:	12/25/2008
Title:	WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS

Patent #:	NONE	Issue Dt:		Application #:	12143157	Filing Dt:	06/20/2008
Publication #:	US20080315407	Pub Dt:	12/25/2008
Title:	THREE-DIMENSIONAL CIRCUITRY FORMED ON INTEGRATED CIRCUIT DEVICE USING TWO-DIMENSIONAL FABRICATION

Patent #:	8629543	Issue Dt:	01/14/2014	Application #:	12913604	Filing Dt:	10/27/2010
Publication #:	US20110037159	Pub Dt:	02/17/2011
Title:	ELECTRICALLY INTERCONNECTED STACKED DIE ASSEMBLIES

Patent #:	8324081	Issue Dt:	12/04/2012	Application #:	13041192	Filing Dt:	03/04/2011
Publication #:	US20110147943	Pub Dt:	06/23/2011
Title:	WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS

Assignor

VERTICAL CIRCUITS, INC.

Exec Dt:

11/14/2012

Assignee

VERTICAL CIRCUITS SOLUTIONS, INC.

10 VICTOR SQUARE

SCOTTS VALLEY, CALIFORNIA USA 95066

Correspondence name and address
	DARYL K. NEFF
	LERNER, DAVID, LITTENBERG, KRUMHOLZ
	& MENTLIK, LLP
	600 SOUTH AVENUE WEST
	WESTFIELD, NJ 07090

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