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Patent #:
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Issue Dt:
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08/26/2008
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Application #:
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10042045
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Filing Dt:
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01/08/2002
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Publication #:
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Pub Dt:
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07/10/2003
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Title:
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DETERMINING A MINIMUM SIZE OF PRESENTATION DATA
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Patent #:
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Issue Dt:
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11/17/2009
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Application #:
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11741164
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Filing Dt:
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04/27/2007
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Publication #:
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Pub Dt:
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10/30/2008
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Title:
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IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION
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Patent #:
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Issue Dt:
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03/09/2010
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Application #:
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11773412
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Filing Dt:
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07/04/2007
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Publication #:
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Pub Dt:
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01/08/2009
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Title:
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CIRCUIT DESIGN OPTIMIZATION OF INTEGRATED CIRCUIT BASED CLOCK GATED MEMORY ELEMENTS
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Patent #:
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Issue Dt:
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06/28/2011
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Application #:
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11778750
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Filing Dt:
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07/17/2007
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Publication #:
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Pub Dt:
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01/22/2009
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Title:
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METHOD, COMPUTER PROGRAM, APPARATUS AND SYSTEM PROVIDING PRINTING FOR AN ILLUMINATION MASK FOR THREE-DIMENSIONAL IMAGES
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Patent #:
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Issue Dt:
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06/15/2010
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Application #:
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11779385
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Filing Dt:
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07/18/2007
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Publication #:
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Pub Dt:
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01/22/2009
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Title:
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SYSTEM AND METHOD FOR INCREASING ERROR CHECKING PERFORMANCE BY CALCULATING CRC CALCULATIONS AFTER MULTIPLE TEST PATTERNS FOR PROCESSOR DESIGN VERIFICATION AND VALIDATION
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Patent #:
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Issue Dt:
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01/12/2010
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Application #:
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11779395
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Filing Dt:
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07/18/2007
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Publication #:
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Pub Dt:
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01/22/2009
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Title:
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SYSTEM AND METHOD OF TESTING USING TEST PATTERN RE-EXECUTION IN VARYING TIMING SCENARIOS FOR PROCESSOR DESIGN VERIFICATION AND VALIDATION
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Patent #:
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Issue Dt:
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12/07/2010
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Application #:
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11828372
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Filing Dt:
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07/26/2007
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Publication #:
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Pub Dt:
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01/29/2009
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Title:
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SYSTEM AND METHOD FOR MODELING STOCHASTIC BEHAVIOR OF A SYSTEM OF N SIMILAR STATISTICAL VARIABLES
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Patent #:
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Issue Dt:
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07/27/2010
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Application #:
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11829179
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Filing Dt:
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07/27/2007
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Publication #:
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Pub Dt:
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01/29/2009
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Title:
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DESIGN METHOD AND SYSTEM FOR MINIMIZING BLIND VIA CURRENT LOOPS
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Patent #:
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Issue Dt:
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11/09/2010
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Application #:
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11830910
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Filing Dt:
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07/31/2007
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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CLOCK DISTRIBUTION NETWORK WIRING STRUCTURE
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Patent #:
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Issue Dt:
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12/28/2010
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Application #:
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11836222
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Filing Dt:
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08/09/2007
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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HARDWARE VERIFICATION BATCH COMPUTING FARM SIMULATOR
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Patent #:
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Issue Dt:
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08/16/2011
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Application #:
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11842337
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Filing Dt:
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08/21/2007
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Publication #:
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Pub Dt:
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02/26/2009
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Title:
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AUGMENTING OF AUTOMATED CLUSTERING-BASED TRACE SAMPLING METHODS BY USER-DIRECTED PHASE DETECTION
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Patent #:
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Issue Dt:
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12/06/2011
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Application #:
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11842491
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Filing Dt:
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08/21/2007
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Publication #:
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Pub Dt:
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02/26/2009
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Title:
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METHOD AND APPARATUS FOR DETECTING CLOCK GATING OPPORTUNITIES IN A PIPELINED ELECTRONIC CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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03/30/2010
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Application #:
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11845056
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Filing Dt:
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08/25/2007
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Publication #:
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Pub Dt:
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02/26/2009
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Title:
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SIMULTANEOUS POWER AND TIMING OPTIMIZATION IN INTEGRATED CIRCUITS BY PERFORMING DISCRETE ACTIONS ON CIRCUIT COMPONENTS
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Patent #:
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Issue Dt:
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05/25/2010
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Application #:
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11845118
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Filing Dt:
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08/27/2007
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Publication #:
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Pub Dt:
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03/05/2009
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Title:
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DEVICE, SYSTEM AND METHOD FOR FORMAL VERIFICATION
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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11846017
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Filing Dt:
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08/28/2007
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Publication #:
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Pub Dt:
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03/05/2009
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Title:
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LAYOUT OPTIMIZATION USING PARAMETERIZED CELLS
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Patent #:
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Issue Dt:
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10/05/2010
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Application #:
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11848821
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Filing Dt:
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08/31/2007
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Publication #:
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Pub Dt:
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03/05/2009
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Title:
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SYSTEMS, METHODS AND COMPUTER PRODUCTS FOR TRAVERSING SCHEMATIC HIERARCHY USING A SCROLLING MECHANISM
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Patent #:
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Issue Dt:
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10/05/2010
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Application #:
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11853573
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Filing Dt:
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09/11/2007
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Publication #:
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Pub Dt:
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03/12/2009
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Title:
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METHOD FOR ELIMINATING NEGATIVE SLACK IN A NETLIST VIA TRANSFORMATION AND SLACK CATEGORIZATION
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Patent #:
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Issue Dt:
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08/31/2010
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Application #:
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11864944
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Filing Dt:
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09/29/2007
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Publication #:
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Pub Dt:
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04/02/2009
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Title:
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SCALABLE DEPENDENT STATE ELEMENT IDENTIFICATION
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Patent #:
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Issue Dt:
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09/28/2010
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Application #:
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11866159
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Filing Dt:
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10/02/2007
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Publication #:
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Pub Dt:
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04/02/2009
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Title:
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METHOD FOR FASTER IDENTIFICATION OF AVAILABLE REFERENCE DESIGNATORS IN A DESIGN AUTOMATION SYSTEM
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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11870471
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Filing Dt:
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10/11/2007
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Publication #:
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Pub Dt:
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04/16/2009
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Title:
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OPTIMAL SIMPLIFICATION OF CONSTRAINT-BASED TESTBENCHES
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Patent #:
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Issue Dt:
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12/28/2010
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Application #:
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11870672
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Filing Dt:
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10/11/2007
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Publication #:
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Pub Dt:
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04/16/2009
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Title:
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METHOD AND APPARATUS FOR INCREMENTALLY COMPUTING CRITICALITY AND YIELD GRADIENT
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Patent #:
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Issue Dt:
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11/02/2010
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Application #:
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11870728
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Filing Dt:
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10/11/2007
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Publication #:
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Pub Dt:
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04/16/2009
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Title:
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BUFFER PLACEMENT WITH RESPECT TO DATA FLOW DIRECTION AND PLACEMENT AREA GEOMETRY IN HIERARCHICAL VLS DESIGNS
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Patent #:
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Issue Dt:
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01/10/2012
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Application #:
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11874950
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Filing Dt:
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10/19/2007
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Publication #:
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Pub Dt:
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04/23/2009
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Title:
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RELIABILITY EVALUATION AND SYSTEM FAIL WARNING METHODS USING ON CHIP PARAMETRIC MONITORS
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Patent #:
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Issue Dt:
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10/18/2011
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Application #:
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11876853
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Filing Dt:
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10/23/2007
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Publication #:
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Pub Dt:
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04/23/2009
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Title:
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METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD
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Patent #:
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Issue Dt:
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02/22/2011
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Application #:
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11927846
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Filing Dt:
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10/30/2007
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Publication #:
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Pub Dt:
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04/30/2009
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Title:
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SYSTEM AND METHOD OF AUTOMATING THE ADDITION OF RTL BASED CRITICAL TIMING PATH COUNTERS TO VERIFY CRITICAL PATH COVERAGE OF POST-SILICON SOFTWARE VALIDATION TOOLS
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Patent #:
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Issue Dt:
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04/12/2011
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Application #:
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11930808
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Filing Dt:
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10/31/2007
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Publication #:
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Pub Dt:
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04/30/2009
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Title:
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Defining and recording threshold-qualified count events of a simulation by testcases
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Patent #:
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Issue Dt:
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11/01/2011
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Application #:
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11930866
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Filing Dt:
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10/31/2007
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Publication #:
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Pub Dt:
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04/30/2009
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Title:
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REPORTING TEMPORAL INFORMATION REGARDING COUNT EVENTS OF A SIMULATION
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Patent #:
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Issue Dt:
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12/21/2010
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Application #:
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11934146
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Filing Dt:
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11/02/2007
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Publication #:
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Pub Dt:
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05/07/2009
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Title:
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SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPROVE PROCESS AND ENVIRONMENTAL PARAMETER SPACE COVERAGE
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Patent #:
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Issue Dt:
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12/14/2010
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11934875
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Filing Dt:
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11/05/2007
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Pub Dt:
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05/07/2009
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Title:
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ARRANGEMENTS FOR DEVELOPING INTEGRATED CIRCUIT DESIGNS
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Issue Dt:
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11/15/2011
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11937073
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11/08/2007
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Pub Dt:
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05/14/2009
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Title:
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OBTAINING BOUNDS ON PROCESS PARAMETERS FOR OPC-VERIFICATION
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Issue Dt:
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09/06/2011
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11938824
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11/13/2007
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Pub Dt:
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05/14/2009
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Title:
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OPTIMAL TIMING-DRIVEN CLONING UNDER LINEAR DELAY MODEL
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04/27/2010
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11939761
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11/14/2007
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Pub Dt:
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05/14/2009
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Title:
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AUTO-ROUTING SMALL JOG ELIMINATOR
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04/27/2010
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11941105
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11/16/2007
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Pub Dt:
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05/21/2009
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Title:
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INCREMENTAL TIMING-DRIVEN, PHYSICAL-SYNTHESIS USING DISCRETE OPTIMIZATION
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11/02/2010
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11941183
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Filing Dt:
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11/16/2007
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Pub Dt:
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05/21/2009
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Title:
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METHOD AND COMPUTER PROGRAM FOR SELECTING CIRCUIT REPAIRS USING REDUNDANT ELEMENTS WITH CONSIDERATION OF AGING EFFECTS
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Patent #:
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Issue Dt:
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07/20/2010
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Application #:
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11941418
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Filing Dt:
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11/16/2007
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Publication #:
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Pub Dt:
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05/21/2009
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Title:
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METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION UNDER A LINEAR DELAY MODEL
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Patent #:
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Issue Dt:
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01/11/2011
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Application #:
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11941998
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Filing Dt:
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11/19/2007
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Pub Dt:
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05/21/2009
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Title:
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METHOD FOR DETERMINING FEATURES ASSOCIATED WITH FAILS OF INTEGRATED CIRCUITS
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Issue Dt:
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02/01/2011
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Application #:
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11945465
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Filing Dt:
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11/27/2007
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Pub Dt:
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05/28/2009
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Title:
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SEQUENTIAL EQUIVALENCE CHECKING FOR ASYNCHRONOUS VERIFICATION
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02/01/2011
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Application #:
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11945754
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Filing Dt:
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11/27/2007
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Publication #:
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Pub Dt:
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05/28/2009
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Title:
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AUTOMATIC VERIFICATION OF ADEQUATE CONDUCTIVE RETURN-CURRENT PATHS
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Issue Dt:
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10/19/2010
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11946937
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11/29/2007
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Pub Dt:
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06/04/2009
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Title:
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AUTOMATED OPTIMIZATION OF DEVICE STRUCTURE DURING CIRCUIT DESIGN STAGE
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Issue Dt:
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02/22/2011
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11958606
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12/18/2007
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Pub Dt:
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06/18/2009
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Title:
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ADAPTIVE WEIGHTING METHOD FOR LAYOUT OPTIMIZATION WITH MULTIPLE PRIORITIES
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Issue Dt:
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05/17/2011
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11961440
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12/20/2007
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06/25/2009
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Title:
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METHOD OF REDUCING CROSSTALK INDUCED NOISE IN CIRCUITRY DESIGNS
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11/09/2010
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11968458
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01/02/2008
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Pub Dt:
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07/02/2009
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Title:
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CA RESISTANCE VARIABILITY PREDICTION METHODOLOGY
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Issue Dt:
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07/12/2011
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11970990
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01/08/2008
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Pub Dt:
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07/09/2009
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Title:
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COMPACT MODEL METHODOLOGY FOR PC LANDING PAD LITHOGRAPHIC ROUNDING IMPACT ON DEVICE PERFORMANCE
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Patent #:
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Issue Dt:
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11/30/2010
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11972747
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01/11/2008
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07/16/2009
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Title:
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METHOD AND APPARATUS FOR EVALUATING INTEGRATED CIRCUIT DESIGN PERFORMANCE USING ENHANCED BASIC BLOCK VECTORS THAT INCLUDE DATA DEPENDENT INFORMATION
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01/11/2011
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11972923
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01/11/2008
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Pub Dt:
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07/16/2009
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Title:
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SYSTEM AND METHOD FOR IMPROVED HIERARCHICAL ANALYSIS OF ELECTRONIC CIRCUITS
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01/18/2011
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12013925
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01/14/2008
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07/16/2009
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Title:
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METHOD AND APPARATUS FOR COMPUTING TEST MARGINS FOR AT-SPEED TESTING
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12/06/2011
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12015084
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01/16/2008
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Publication #:
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Pub Dt:
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07/16/2009
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Title:
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RENDERING A MASK USING COARSE MASK REPRESENTATION
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Issue Dt:
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11/15/2011
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12015768
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01/17/2008
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Publication #:
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Pub Dt:
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07/23/2009
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Title:
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CALCULATING IMAGE INTENSITY OF MASK BY DECOMPOSING MANHATTAN POLYGON BASED ON PARALLEL EDGE
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Patent #:
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Issue Dt:
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03/08/2011
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12018422
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01/23/2008
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Pub Dt:
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07/23/2009
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Title:
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PLACEMENT DRIVEN ROUTING
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Issue Dt:
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12/07/2010
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12021363
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01/29/2008
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Publication #:
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Pub Dt:
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07/30/2009
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Title:
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AUTO-ROUTER PERFORMING SIMULTANEOUS PLACEMENT OF SIGNAL AND RETURN PATHS
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Patent #:
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Issue Dt:
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08/02/2011
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12021670
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Filing Dt:
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01/29/2008
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Publication #:
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Pub Dt:
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07/30/2009
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Title:
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TECHNIQUES FOR FILTERING SYSTEMATIC DIFFERENCES FROM WAFER EVALUATION PARAMETERS
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Issue Dt:
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09/13/2011
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12021723
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01/29/2008
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Publication #:
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Pub Dt:
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07/30/2009
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Title:
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MULTIPLE VOLTAGE THRESHOLD TIMING ANALYSIS FOR A DIGITAL INTEGRATED CIRCUIT
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08/13/2009
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08/13/2009
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08/20/2009
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08/20/2009
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08/27/2009
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08/27/2009
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08/27/2009
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08/27/2009
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09/10/2009
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11/30/2010
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09/17/2009
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08/23/2011
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09/17/2009
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09/24/2009
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09/24/2009
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09/24/2009
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11/16/2010
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09/24/2009
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04/21/2009
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03/31/2008
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10/15/2009
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11/05/2009
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03/10/2009
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04/30/2008
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11/05/2009
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