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Patent Assignment Details
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Reel/Frame:029736/0944   Pages: 10
Recorded: 01/30/2013
Attorney Dkt #:TIPI 5.2-036
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 26
1
Patent #:
5675180
Issue Dt:
10/07/1997
Application #:
08265081
Filing Dt:
06/23/1994
Title:
VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS
2
Patent #:
5657206
Issue Dt:
08/12/1997
Application #:
08374421
Filing Dt:
01/19/1995
Title:
A CONDUCTIVE EXPOXY FLIP-CHIP PACKAGE AND METHOD
3
Patent #:
5698895
Issue Dt:
12/16/1997
Application #:
08376149
Filing Dt:
01/20/1995
Title:
SILICON SEGMENT PROGRAMMING METHOD AND APPARATUS
4
Patent #:
5661087
Issue Dt:
08/26/1997
Application #:
08476623
Filing Dt:
06/07/1995
Title:
VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS
5
Patent #:
6134118
Issue Dt:
10/17/2000
Application #:
08834798
Filing Dt:
04/03/1997
Title:
CONDUCTIVE EPOXY FLIP-CHIP PACKAGE AND METHOD
6
Patent #:
6188126
Issue Dt:
02/13/2001
Application #:
08842448
Filing Dt:
04/24/1997
Title:
VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS
7
Patent #:
5994170
Issue Dt:
11/30/1999
Application #:
08845654
Filing Dt:
04/25/1997
Title:
SILICON SEGMENT PROGRAMMING METHOD
8
Patent #:
5936302
Issue Dt:
08/10/1999
Application #:
08845655
Filing Dt:
04/25/1997
Title:
SPEAKER DIAPHRAGM
9
Patent #:
5837566
Issue Dt:
11/17/1998
Application #:
08847309
Filing Dt:
04/24/1997
Title:
VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS
10
Patent #:
6255726
Issue Dt:
07/03/2001
Application #:
08915620
Filing Dt:
08/21/1997
Title:
VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION
11
Patent #:
6098278
Issue Dt:
08/08/2000
Application #:
08917447
Filing Dt:
08/22/1997
Title:
METHOD FOR FORMING CONDUCTIVE EPOXY FLIP-CHIP ON CHIP
12
Patent #:
6271598
Issue Dt:
08/07/2001
Application #:
08918500
Filing Dt:
08/22/1997
Title:
CONDUCTIVE EPOXY FLIP-CHIP ON CHIP
13
Patent #:
6124633
Issue Dt:
09/26/2000
Application #:
08918501
Filing Dt:
08/22/1997
Title:
VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM
14
Patent #:
5891761
Issue Dt:
04/06/1999
Application #:
08918502
Filing Dt:
08/22/1997
Title:
METHOD FOR FORMING VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH THERMALLY CONDUCTIVE EPOXY PREFORM
15
Patent #:
6080596
Issue Dt:
06/27/2000
Application #:
08920273
Filing Dt:
08/22/1997
Title:
METHOD FOR FORMING VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION
16
Patent #:
6486528
Issue Dt:
11/26/2002
Application #:
09378879
Filing Dt:
08/23/1999
Title:
SILICON SEGMENT PROGRAMMING APPARATUS AND THREE TERMINAL FUSE CONFIGURATION
17
Patent #:
7705432
Issue Dt:
04/27/2010
Application #:
11016558
Filing Dt:
12/17/2004
Publication #:
US20050224952
Pub Dt:
10/13/2005
Title:
THREE DIMENSIONAL SIX SURFACE CONFORMAL DIE COATING
18
Patent #:
7215018
Issue Dt:
05/08/2007
Application #:
11090969
Filing Dt:
03/25/2005
Publication #:
US20050230802
Pub Dt:
10/20/2005
Title:
STACKED DIE BGA OR LGA COMPONENT ASSEMBLY
19
Patent #:
7245021
Issue Dt:
07/17/2007
Application #:
11097829
Filing Dt:
03/31/2005
Publication #:
US20050258530
Pub Dt:
11/24/2005
Title:
MICROPEDE STACKED DIE COMPONENT ASSEMBLY
20
Patent #:
8357999
Issue Dt:
01/22/2013
Application #:
11744142
Filing Dt:
05/03/2007
Publication #:
US20070284716
Pub Dt:
12/13/2007
Title:
ASSEMBLY HAVING STACKED DIE MOUNTED ON SUBSTRATE
21
Patent #:
7535109
Issue Dt:
05/19/2009
Application #:
11744153
Filing Dt:
05/03/2007
Publication #:
US20070252262
Pub Dt:
11/01/2007
Title:
DIE ASSEMBLY HAVING ELECTRICAL INTERCONNECT
22
Patent #:
8742602
Issue Dt:
06/03/2014
Application #:
12046651
Filing Dt:
03/12/2008
Publication #:
US20080224279
Pub Dt:
09/18/2008
Title:
VERTICAL ELECTRICAL INTERCONNECT FORMED ON SUPPORT PRIOR TO DIE MOUNT
23
Patent #:
8723332
Issue Dt:
05/13/2014
Application #:
12124077
Filing Dt:
05/20/2008
Publication #:
US20080303131
Pub Dt:
12/11/2008
Title:
ELECTRICALLY INTERCONNECTED STACKED DIE ASSEMBLIES
24
Patent #:
7923349
Issue Dt:
04/12/2011
Application #:
12142589
Filing Dt:
06/19/2008
Publication #:
US20080315434
Pub Dt:
12/25/2008
Title:
WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS
25
Patent #:
8629543
Issue Dt:
01/14/2014
Application #:
12913604
Filing Dt:
10/27/2010
Publication #:
US20110037159
Pub Dt:
02/17/2011
Title:
ELECTRICALLY INTERCONNECTED STACKED DIE ASSEMBLIES
26
Patent #:
8324081
Issue Dt:
12/04/2012
Application #:
13041192
Filing Dt:
03/04/2011
Publication #:
US20110147943
Pub Dt:
06/23/2011
Title:
WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS
Assignor
1
VERTICAL CIRCUITS (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Exec Dt:
11/09/2012
Assignee
1
INVENSAS CORPORATION
2702 ORCHARD PARKWAY
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
DARYL K. NEFF
LERNER, DAVID, LITTENBERG
KRUMHOLZ & MENTLIK, LLP
600 SOUTH AVENUE WEST
WESTFIELD, NJ 07090

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