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Reel/Frame:030049/0831   Pages: 4
Recorded: 03/20/2013
Attorney Dkt #:ELPIDA GROUP C
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 11
1
Patent #:
Issue Dt:
10/06/2009
Application #:
11299731
Filing Dt:
12/13/2005
Publication #:
Pub Dt:
06/22/2006
Title:
SEMICONDUCTOR DEVICE HAVING A SILICON LAYER IN A GATE ELECTRODE
2
Patent #:
Issue Dt:
11/18/2008
Application #:
11366433
Filing Dt:
03/03/2006
Publication #:
Pub Dt:
09/07/2006
Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PLANARIZED INTERLAYER INSULATING FILM
3
Patent #:
Issue Dt:
12/15/2009
Application #:
11372351
Filing Dt:
03/10/2006
Publication #:
Pub Dt:
11/09/2006
Title:
SEMICONDUCTOR CHIP WITH A POROUS SINGLE CRYSTAL LAYER AND MANUFACTURING METHOD OF THE SAME
4
Patent #:
Issue Dt:
06/15/2010
Application #:
11514934
Filing Dt:
09/05/2006
Publication #:
Pub Dt:
03/08/2007
Title:
METHOD FOR CONTROLLING THICKNESS DISTRIBUTION OF A FILM
5
Patent #:
Issue Dt:
11/17/2009
Application #:
11598644
Filing Dt:
11/14/2006
Publication #:
Pub Dt:
05/15/2008
Title:
MANUFACTURING METHOD FOR INCREASING PRODUCT YIELD OF MEMORY DEVICES SUFFERING FROM SOURCE/DRAIN JUNCTION LEAKAGE
6
Patent #:
Issue Dt:
09/22/2009
Application #:
11833894
Filing Dt:
08/03/2007
Publication #:
Pub Dt:
02/07/2008
Title:
METHOD FOR FORMING A NITROGEN-CONTAINING GATE INSULATING FILM
7
Patent #:
Issue Dt:
07/28/2009
Application #:
11870045
Filing Dt:
10/10/2007
Publication #:
Pub Dt:
04/17/2008
Title:
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTIONS HAVING A SMALLER WIDTH
8
Patent #:
Issue Dt:
07/26/2011
Application #:
11928459
Filing Dt:
10/30/2007
Publication #:
Pub Dt:
05/29/2008
Title:
CALIBRATION CIRCUIT
9
Patent #:
Issue Dt:
07/21/2009
Application #:
12071971
Filing Dt:
02/28/2008
Publication #:
Pub Dt:
09/04/2008
Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
10
Patent #:
Issue Dt:
06/08/2010
Application #:
12213624
Filing Dt:
06/23/2008
Publication #:
Pub Dt:
10/30/2008
Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
11
Patent #:
Issue Dt:
01/25/2011
Application #:
12453737
Filing Dt:
05/20/2009
Publication #:
Pub Dt:
09/17/2009
Title:
SEMICONDUCTOR DEVICE HAVING SILICON LAYER IN A GATE ELECTRODE
Assignor
1
Exec Dt:
03/06/2013
Assignee
1
1050 ENTERPRISE WAY, SUITE 700
SUNNYVALE, CALIFORNIA 94089
Correspondence name and address
TARISA WAIN
1050 ENTERPRISE WAY #700
SUNNYVALE, CA 94089

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