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Reel/Frame:030798/0964   Pages: 2
Recorded: 07/15/2013
Attorney Dkt #:TSM13-0497
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
11/25/2014
Application #:
13942177
Filing Dt:
07/15/2013
Title:
METHOD FOR DISPLAYING TIMING INFORMATION OF AN INTEGRATED CIRCUIT FLOORPLAN
Assignors
1
Exec Dt:
07/10/2013
2
Exec Dt:
07/10/2013
3
Exec Dt:
07/10/2013
Assignee
1
NO. 8, LI-HSIN RD. 6
SCIENCE-BASED INDUSTRIAL PARK
HSIN-CHU, TAIWAN 300-77
Correspondence name and address
SLATER & MATSIL, L.L.P.
17950 PRESTON ROAD, SUITE 1000
DALLAS, TX 75252

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