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Patent Assignment Details
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Reel/Frame:031956/0680   Pages: 5
Recorded: 01/14/2014
Attorney Dkt #:MRIGI
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 7
1
Patent #:
Issue Dt:
06/17/2003
Application #:
09760640
Filing Dt:
01/17/2001
Publication #:
Pub Dt:
06/21/2001
Title:
MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
2
Patent #:
Issue Dt:
11/09/2004
Application #:
10443826
Filing Dt:
05/23/2003
Publication #:
Pub Dt:
05/13/2004
Title:
MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
3
Patent #:
Issue Dt:
12/12/2006
Application #:
10837596
Filing Dt:
05/04/2004
Publication #:
Pub Dt:
10/14/2004
Title:
MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
4
Patent #:
Issue Dt:
10/28/2008
Application #:
11582982
Filing Dt:
10/19/2006
Publication #:
Pub Dt:
02/15/2007
Title:
MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
5
Patent #:
Issue Dt:
01/05/2010
Application #:
12236914
Filing Dt:
09/24/2008
Publication #:
Pub Dt:
04/30/2009
Title:
MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
6
Patent #:
Issue Dt:
03/22/2011
Application #:
12631592
Filing Dt:
12/04/2009
Publication #:
Pub Dt:
04/01/2010
Title:
MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
7
Patent #:
Issue Dt:
02/07/2012
Application #:
13022950
Filing Dt:
02/08/2011
Publication #:
Pub Dt:
06/02/2011
Title:
MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
Assignors
1
Exec Dt:
07/08/1998
2
Exec Dt:
07/08/1998
3
Exec Dt:
07/08/1998
4
Exec Dt:
07/08/1998
Assignee
1
1-1,SAIWAI-CHO,TAKATSUKI-SHI
OSAKA, JAPAN 569-1193
Correspondence name and address
PANASONIC CORPORATION
2-1-61, SHIROMI, CHUO-KU
7F OBP PANASONIC TOWER
OSAKA, 540-6207 JAPAN

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