Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 031956/0680 | |
| Pages: | 5 |
| | Recorded: | 01/14/2014 | | |
Attorney Dkt #: | MRIGI |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
7
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09760640
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Filing Dt:
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01/17/2001
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Publication #:
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Pub Dt:
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06/21/2001
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Title:
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MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10443826
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Filing Dt:
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05/23/2003
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Publication #:
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Pub Dt:
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05/13/2004
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Title:
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MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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10837596
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Filing Dt:
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05/04/2004
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Publication #:
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Pub Dt:
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10/14/2004
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Title:
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MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
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Patent #:
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Issue Dt:
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10/28/2008
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Application #:
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11582982
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Filing Dt:
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10/19/2006
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Publication #:
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Pub Dt:
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02/15/2007
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Title:
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MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
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Patent #:
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Issue Dt:
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01/05/2010
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Application #:
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12236914
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Filing Dt:
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09/24/2008
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Publication #:
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Pub Dt:
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04/30/2009
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Title:
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MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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12631592
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Filing Dt:
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12/04/2009
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Publication #:
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Pub Dt:
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04/01/2010
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Title:
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MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
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Patent #:
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Issue Dt:
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02/07/2012
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Application #:
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13022950
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Filing Dt:
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02/08/2011
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Publication #:
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Pub Dt:
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06/02/2011
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Title:
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MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION
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Assignee
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1-1,SAIWAI-CHO,TAKATSUKI-SHI |
OSAKA, JAPAN 569-1193 |
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Correspondence name and address
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PANASONIC CORPORATION
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2-1-61, SHIROMI, CHUO-KU
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7F OBP PANASONIC TOWER
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OSAKA, 540-6207 JAPAN
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