Patent Assignment Details
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| Reel/Frame: | 032473/0888 | |
| Pages: | 5 |
| | Recorded: | 03/19/2014 | | |
| Attorney Dkt #: | ELPIDA TRANSFER |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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05/12/2015
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Application #:
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12510633
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Filing Dt:
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07/28/2009
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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MEMORY DEVICE WITH PIN REGISTER TO SET INPUT/OUTPUT DIRECTION AND BITWIDTH OF DATA SIGNALS.
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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13327057
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Filing Dt:
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12/15/2011
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Publication #:
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Pub Dt:
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06/20/2013
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Title:
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WIRING CONFIGURATION OF A BUS SYSTEM AND POWER WIRES IN A MEMORY CHIP
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Patent #:
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Issue Dt:
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06/10/2014
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Application #:
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13782300
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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02/06/2014
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Title:
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METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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08/06/2019
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Application #:
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14162282
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Filing Dt:
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01/23/2014
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Publication #:
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Pub Dt:
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07/23/2015
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Title:
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OVERHEAT PROTECTION CIRCUIT AND METHOD IN AN ACCELERATED AGING TEST OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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12/05/2017
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Application #:
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14166413
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Filing Dt:
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01/28/2014
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Publication #:
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Pub Dt:
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07/31/2014
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Title:
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APPARATUS AND METHOD OF PRE-CHARGE AND EQUALIZATION CONTROL FOR DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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05/02/2017
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Application #:
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14168899
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Filing Dt:
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01/30/2014
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Publication #:
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Pub Dt:
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05/28/2015
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Title:
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PARTIAL ACCESS MODE FOR DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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14169442
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Filing Dt:
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01/31/2014
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Publication #:
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Pub Dt:
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08/21/2014
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Title:
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SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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12/20/2016
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Application #:
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14169659
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Filing Dt:
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01/31/2014
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Publication #:
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Pub Dt:
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08/21/2014
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Title:
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APPARATUSES AND METHODS FOR COUPLING SEMICONDUCTOR DEVICES OF A MEMORY MODULE IN A MEMORY SYSTEM
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Assignee
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| 8000 SOUTH FEDERAL WAY |
| BOISE, IDAHO 83716-9632 |
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Correspondence name and address
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DORSEY & WHITNEY LLP
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701 5TH AVENUE, SUITE 6100
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SEATTLE, WA 98104
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