|
Total properties:
25
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
08003000
|
Filing Dt:
|
01/11/1993
|
|
Title:
|
METHOD AND APPARATUS FOR USER SIDE SCHEDULING IN A MULTIPROCESSOR OPERATING SYSTEM PROGRAM THAT IMPLEMENTS DISTRIBUTIVE SCHEDULING OF PROCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/1996
|
Application #:
|
08128720
|
Filing Dt:
|
09/30/1993
|
|
Title:
|
SYSTEM AND METHOD FOR GENERATING A READ-MODIFY-WRITE OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/1996
|
Application #:
|
08165379
|
Filing Dt:
|
12/10/1993
|
|
Title:
|
METHOD FOR THE DYNAMIC ALLOCATION OF ARRAY SIZES IN A MULTIPROCESSOR SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08205990
|
Filing Dt:
|
03/04/1994
|
|
Title:
|
ARRANGEMENT FOR MODIFYING ELECTRICAL PRINTED CIRCUIT BOARDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08521566
|
Filing Dt:
|
08/30/1995
|
|
Title:
|
VECTOR WORD SHIFT BY VO SHIFT COUNT IN VECTOR SUPERCOMPUTER PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
08539524
|
Filing Dt:
|
10/06/1995
|
|
Title:
|
SYSTEM AND MERTHOD FOR UNCACHED STORE BUFFERING IN A MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/1998
|
Application #:
|
08544537
|
Filing Dt:
|
10/18/1995
|
|
Title:
|
ACKNOWLEDGE TRIGGERED FORWARDING OF EXTERNAL BLOCK DATA RESPONSES IN A MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
08550992
|
Filing Dt:
|
10/31/1995
|
|
Title:
|
VIRTUAL MAINTENANCE NETWORK IN MULTIPROCESSING SYSTEM HAVING A NON- FLOW CONTROLLED VIRTUAL MAINTENANCE CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/1998
|
Application #:
|
08589532
|
Filing Dt:
|
01/22/1996
|
|
Title:
|
PROCESSOR-INCLUSIVE MEMORY MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/1998
|
Application #:
|
08592736
|
Filing Dt:
|
01/26/1996
|
|
Title:
|
SYSTEM AND METHOD TO REDUCE PHASE OFFSET AND PHASE JITTER IN PHASE-LOCKED AND DELAY-LOCKED LOOPS USING SELF-BIASED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
08606291
|
Filing Dt:
|
02/23/1996
|
|
Title:
|
BGA LAND PATTERN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/1998
|
Application #:
|
08638186
|
Filing Dt:
|
04/26/1996
|
|
Title:
|
MULTI-CONFIGURABLE PUSH-PULL/OPEN-DRAIN DRIVER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/1998
|
Application #:
|
08688501
|
Filing Dt:
|
07/29/1996
|
|
Title:
|
APPARATUS AND METHOD FOR DYNAMIC CENTRAL PROCESSING UNIT CLOCK ADJUSTMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1999
|
Application #:
|
08706808
|
Filing Dt:
|
09/03/1996
|
|
Title:
|
DENSITY DEPENDENT VECTOR MASK OPERATION CONTROL APPARATUS AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/1999
|
Application #:
|
08708298
|
Filing Dt:
|
09/04/1996
|
|
Title:
|
METHOD TO PIPELINE WRITE MISSES IN SHARED CACHE MULTIPROCESSOR SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/1998
|
Application #:
|
08713283
|
Filing Dt:
|
09/12/1996
|
|
Title:
|
COMPRESSION CONNECTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/1997
|
Application #:
|
08747976
|
Filing Dt:
|
11/12/1996
|
|
Title:
|
DIMM PAIR WITH DATA MEMORY AND STATE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
08789557
|
Filing Dt:
|
01/27/1997
|
|
Title:
|
PROCESSOR-INCLUSIVE MEMORY MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
08903042
|
Filing Dt:
|
07/29/1997
|
|
Title:
|
PROCESSOR-INCLUSIVE MEMORY MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
08927359
|
Filing Dt:
|
09/09/1997
|
|
Title:
|
STOP ALIGN LATERAL MODULE TO MODULE INTERCONNECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
08934973
|
Filing Dt:
|
09/22/1997
|
|
Title:
|
DEMATEABLE, COMPLIANT, AREA ARRAY INTERCONNECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09055677
|
Filing Dt:
|
04/06/1998
|
|
Title:
|
SYSTEM AND FOR STACKING OF INTEGRATED CIRCUIT PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09138613
|
Filing Dt:
|
08/24/1998
|
|
Title:
|
VECTOR SHIFT FUNCTIONAL UNIT FOR SUCCESSIVELY SHIFTING OPERANDS STORED IN A VECTOR REGISTER BY CORRESPONDING SHIFT COUNTS STORED IN ANOTHER VECTOR REGISTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09174862
|
Filing Dt:
|
10/19/1998
|
|
Title:
|
ARRAY ADDRESS AND LOOP ALIGNMENT CALCULATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09346659
|
Filing Dt:
|
07/01/1999
|
|
Title:
|
DESIGN FOR CIRCUIT BOARD ORTHOGONAL INSTALLATION AND REMOVAL
|
|
