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Reel/Frame:032856/0031   Pages: 443
Recorded: 05/08/2014
Attorney Dkt #:040981-0072
Conveyance: PATENT SECURITY AGREEMENT
Total properties: 11127
Page 53 of 112
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112
1
Patent #:
6538592
Issue Dt:
03/25/2003
Application #:
09962630
Filing Dt:
09/24/2001
Title:
VARIABLE DYNAMIC RANGE ANALOG-TO-DIGITAL CONVERTER
2
Patent #:
6495875
Issue Dt:
12/17/2002
Application #:
09962641
Filing Dt:
09/25/2001
Publication #:
US20020017670
Pub Dt:
02/14/2002
Title:
METHOD OF FORMING METAL OXIDE METAL CAPACITORS USING MULTI-STEP RAPID MATERIAL THERMAL PROCESS AND A DEVICE FORMED THEREBY
3
Patent #:
6721826
Issue Dt:
04/13/2004
Application #:
09962645
Filing Dt:
09/25/2001
Publication #:
US20030061413
Pub Dt:
03/27/2003
Title:
BUFFER PARTITIONING FOR MANAGING MULTIPLE DATA STREAMS
4
Patent #:
6643832
Issue Dt:
11/04/2003
Application #:
09964011
Filing Dt:
09/26/2001
Title:
VIRTUAL TREE-BASED NETLIST MODEL AND METHOD OF DELAY ESTIMATION FOR AN INTEGRATED CIRCUIT DESIGN
5
Patent #:
7020589
Issue Dt:
03/28/2006
Application #:
09964030
Filing Dt:
09/26/2001
Title:
METHOD AND APPARATUS FOR ADAPTIVE TIMING OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN
6
Patent #:
6737311
Issue Dt:
05/18/2004
Application #:
09964041
Filing Dt:
09/26/2001
Publication #:
US20030057494
Pub Dt:
03/27/2003
Title:
SEMICONDUCTOR DEVICE HAVING A BURIED LAYER FOR REDUCING LATCHUP AND A METHOD OF MANUFACTURE THEREFOR
7
Patent #:
6731448
Issue Dt:
05/04/2004
Application #:
09964083
Filing Dt:
09/26/2001
Publication #:
US20030058566
Pub Dt:
03/27/2003
Title:
ACCURATE RESISTANCE MEASUREMENT FOR MAGNETORESISTIVE HEAD
8
Patent #:
6621146
Issue Dt:
09/16/2003
Application #:
09964157
Filing Dt:
09/26/2001
Title:
METHOD AND APPARATUS FOR THE USE OF EMBEDDED RESISTANCE TO LINEARIZE AND IMPROVE THE MATCHING PROPERTIES OF TRANSISTORS
9
Patent #:
6764930
Issue Dt:
07/20/2004
Application #:
09964227
Filing Dt:
09/26/2001
Publication #:
US20030057465
Pub Dt:
03/27/2003
Title:
METHOD AND STRUCTURE FOR MODULAR, HIGHLY LINEAR MOS CAPACITORS USING NITROGEN IMPLANTATION
10
Patent #:
6573183
Issue Dt:
06/03/2003
Application #:
09965739
Filing Dt:
09/28/2001
Publication #:
US20030064586
Pub Dt:
04/03/2003
Title:
METHOD AND APPARATUS FOR CONTROLLING CONTAMINATION DURING THE ELECTROPLATING DEPOSITION OF METALS ONTO A SEMICONDUCTOR WAFER SURFACE
11
Patent #:
6366530
Issue Dt:
04/02/2002
Application #:
09965947
Filing Dt:
09/28/2001
Title:
SYNCHRONIZING DATA OPERATIONS ACROSS A SYNCHRONIZATION BOUNDARY BETWEEN DIFFERENT CLOCK DOMAINS USING TWO-HOT ENCODING
12
Patent #:
6512550
Issue Dt:
01/28/2003
Application #:
09965948
Filing Dt:
09/28/2001
Title:
MOTION COMPENSATED DE-INTERLACING
13
Patent #:
6695572
Issue Dt:
02/24/2004
Application #:
09966156
Filing Dt:
09/28/2001
Publication #:
US20030063967
Pub Dt:
04/03/2003
Title:
METHOD AND APPARATUS FOR MINIMIZING SEMICONDUCTOR WAFER CONTAMINATION
14
Patent #:
7119627
Issue Dt:
10/10/2006
Application #:
09966204
Filing Dt:
09/28/2001
Publication #:
US20020044023
Pub Dt:
04/18/2002
Title:
PHASE-LOCKED LOOP CIRCUIT AS WELL AS A VOLTAGE-CONTROLLED OSCILLATOR AS USED IN A PHASE-LOCKED LOOP CIRCUIT
15
Patent #:
7043670
Issue Dt:
05/09/2006
Application #:
09966327
Filing Dt:
09/28/2001
Publication #:
US20020121918
Pub Dt:
09/05/2002
Title:
REDUCING THE EFFECT OF SIMULTANEOUS SWITCHING NOISE
16
Patent #:
6576544
Issue Dt:
06/10/2003
Application #:
09966464
Filing Dt:
09/28/2001
Title:
METHOD OF FABRICATING A LOCAL INTERCONNECT
17
Patent #:
6736953
Issue Dt:
05/18/2004
Application #:
09966651
Filing Dt:
09/28/2001
Title:
HIGH FREQUENCY ELECTROCHEMICAL DEPOSITION
18
Patent #:
6548422
Issue Dt:
04/15/2003
Application #:
09966779
Filing Dt:
09/27/2001
Publication #:
US20030060058
Pub Dt:
03/27/2003
Title:
METHOD AND STRUCTURE FOR OXIDE/SILICON NITRIDE INTERFACE SUBSTRUCTURE IMPROVEMENTS
19
Patent #:
6892277
Issue Dt:
05/10/2005
Application #:
09966867
Filing Dt:
09/28/2001
Title:
SYSTEM AND METHOD FOR OPTIMIZING REMOTE DATA CONTENT DISTRIBUTION
20
Patent #:
6727165
Issue Dt:
04/27/2004
Application #:
09967074
Filing Dt:
09/28/2001
Title:
FABRICATION OF METAL CONTACTS FOR DEEP-SUBMICRON TECHNOLOGIES
21
Patent #:
7071563
Issue Dt:
07/04/2006
Application #:
09967094
Filing Dt:
09/28/2001
Publication #:
US20030062626
Pub Dt:
04/03/2003
Title:
BARRIER LAYER FOR INTERCONNECT STRUCTURES OF A SEMICONDUCTOR WAFER AND METHOD FOR DEPOSITING THE BARRIER LAYER
22
Patent #:
6651226
Issue Dt:
11/18/2003
Application #:
09967114
Filing Dt:
09/28/2001
Publication #:
US20020170021
Pub Dt:
11/14/2002
Title:
PROCESS CONTROL USING THREE DIMENSIONAL RECONSTRUCTION METROLOGY
23
Patent #:
6714892
Issue Dt:
03/30/2004
Application #:
09967119
Filing Dt:
09/28/2001
Publication #:
US20020156594
Pub Dt:
10/24/2002
Title:
THREE DIMENSIONAL RECONSTRUCTION METROLOGY
24
Patent #:
7039435
Issue Dt:
05/02/2006
Application #:
09967140
Filing Dt:
09/28/2001
Publication #:
US20030064732
Pub Dt:
04/03/2003
Title:
PROXIMITY REGULATION SYSTEM FOR USE WITH A PORTABLE CELL PHONE AND A METHOD OF OPERATION THEREOF
25
Patent #:
6496081
Issue Dt:
12/17/2002
Application #:
09967195
Filing Dt:
09/28/2001
Title:
TRANSMISSION EQUALIZATION SYSTEM AND AN INTEGRATED CIRCUIT PACKAGE EMPLOYING THE SAME
26
Patent #:
6639710
Issue Dt:
10/28/2003
Application #:
09967216
Filing Dt:
09/29/2001
Publication #:
US20030063401
Pub Dt:
04/03/2003
Title:
METHOD AND APPARATUS FOR THE CORRECTION OF OPTICAL SIGNAL WAVE FRONT DISTORTION USING ADAPTIVE OPTICS
27
Patent #:
6641746
Issue Dt:
11/04/2003
Application #:
09967435
Filing Dt:
09/28/2001
Publication #:
US20030062339
Pub Dt:
04/03/2003
Title:
CONTROL OF SEMICONDUCTOR PROCESSING
28
Patent #:
6907590
Issue Dt:
06/14/2005
Application #:
09968008
Filing Dt:
10/02/2001
Title:
INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
29
Patent #:
6907586
Issue Dt:
06/14/2005
Application #:
09968009
Filing Dt:
10/02/2001
Title:
INTERGRATED DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
30
Patent #:
6709904
Issue Dt:
03/23/2004
Application #:
09968234
Filing Dt:
09/28/2001
Publication #:
US20030064567
Pub Dt:
04/03/2003
Title:
VERTICAL REPLACEMENT-GATE SILICON-ON-INSULATOR TRANSISTOR
31
Patent #:
6607927
Issue Dt:
08/19/2003
Application #:
09968243
Filing Dt:
09/28/2001
Publication #:
US20030064533
Pub Dt:
04/03/2003
Title:
METHOD AND APPARATUS FOR MONITORING IN-LINE COPPER CONTAMINATION
32
Patent #:
6657870
Issue Dt:
12/02/2003
Application #:
09968286
Filing Dt:
10/01/2001
Title:
DIE POWER DISTRIBUTION SYSTEM
33
Patent #:
7006627
Issue Dt:
02/28/2006
Application #:
09968476
Filing Dt:
09/28/2001
Publication #:
US20030063741
Pub Dt:
04/03/2003
Title:
CIPHER BLOCK CHAINING MODE IN ENCRYPTION/DECRYPTION PROCESSING
34
Patent #:
6472314
Issue Dt:
10/29/2002
Application #:
09968944
Filing Dt:
10/02/2001
Title:
METHOD OF MAKING INTERCONNECT STRUCTURE INCLUDING DIAMOND BARRIER LAYER
35
Patent #:
6859886
Issue Dt:
02/22/2005
Application #:
09969377
Filing Dt:
10/02/2001
Title:
IO BASED EMBEDDED PROCESSOR CLOCK SPEED CONTROL
36
Patent #:
7183623
Issue Dt:
02/27/2007
Application #:
09970074
Filing Dt:
10/02/2001
Publication #:
US20030062591
Pub Dt:
04/03/2003
Title:
TRIMMED INTEGRATED CIRCUITS WITH FUSE CIRCUITS
37
Patent #:
6647348
Issue Dt:
11/11/2003
Application #:
09970392
Filing Dt:
10/03/2001
Publication #:
US20030069706
Pub Dt:
04/10/2003
Title:
LATENT DEFECT CLASSIFICATION SYSTEM
38
Patent #:
6472316
Issue Dt:
10/29/2002
Application #:
09971329
Filing Dt:
10/04/2001
Title:
PHOTOLITHOGRAPHY OVERLAY CONTROL
39
Patent #:
6792579
Issue Dt:
09/14/2004
Application #:
09972100
Filing Dt:
10/05/2001
Publication #:
US20030084410
Pub Dt:
05/01/2003
Title:
SPICE TO VERILOG NETLIST TRANSLATOR AND DESIGN METHODS USING SPICE TO VERILOG AND VERILOG TO SPICE TRANSLATION
40
Patent #:
7111301
Issue Dt:
09/19/2006
Application #:
09972330
Filing Dt:
10/05/2001
Title:
REQUEST AND COMPLETION QUEUE LOAD BALANCING
41
Patent #:
6667536
Issue Dt:
12/23/2003
Application #:
09972481
Filing Dt:
10/05/2001
Publication #:
US20030003603
Pub Dt:
01/02/2003
Title:
THIN FILM MULTI-LAYER HIGH Q TRANSFORMER FORMED IN A SEMICONDUCTOR SUBSTRATE
42
Patent #:
6639298
Issue Dt:
10/28/2003
Application #:
09972482
Filing Dt:
10/05/2001
Publication #:
US20030001231
Pub Dt:
01/02/2003
Title:
MULTI-LAYER INDUCTOR FORMED IN A SEMICONDUCTOR SUBSTRATE
43
Patent #:
7051318
Issue Dt:
05/23/2006
Application #:
09973153
Filing Dt:
10/09/2001
Title:
WEB BASED OLA MEMORY GENERATOR
44
Patent #:
6766406
Issue Dt:
07/20/2004
Application #:
09973267
Filing Dt:
10/08/2001
Title:
FIELD PROGRAMMABLE UNIVERSAL SERIAL BUS APPLICATION SPECIFIC INTEGRATED CIRCUIT AND METHOD OF OPERATION THEREOF
45
Patent #:
6658361
Issue Dt:
12/02/2003
Application #:
09974008
Filing Dt:
10/10/2001
Title:
HEAVIEST ONLY FAIL POTENTIAL
46
Patent #:
6618938
Issue Dt:
09/16/2003
Application #:
09974157
Filing Dt:
10/09/2001
Title:
INTERPOSER FOR SEMICONDUCTOR PACKAGE ASSEMBLY
47
Patent #:
6513376
Issue Dt:
02/04/2003
Application #:
09974251
Filing Dt:
10/10/2001
Title:
LIQUID LEVEL HEIGHT MEASUREMENT SYSTEM
48
Patent #:
7117420
Issue Dt:
10/03/2006
Application #:
09975293
Filing Dt:
10/11/2001
Title:
CONSTRUCTION OF AN OPTIMIZED SEC-DED CODE AND LOGIC FOR SOFT ERRORS IN SEMICONDUCTOR MEMORIES
49
Patent #:
7218681
Issue Dt:
05/15/2007
Application #:
09975682
Filing Dt:
10/11/2001
Publication #:
US20030072380
Pub Dt:
04/17/2003
Title:
METHOD AND APPARATUS FOR CROSS-TALK MITIGATION THROUGH JOINT MULTIUSER ADAPTIVE PRE-CODING
50
Patent #:
6874056
Issue Dt:
03/29/2005
Application #:
09975762
Filing Dt:
10/09/2001
Publication #:
US20030070045
Pub Dt:
04/10/2003
Title:
METHOD AND APPARATUS FOR REDUCING CACHE THRASHING
51
Patent #:
6874057
Issue Dt:
03/29/2005
Application #:
09975763
Filing Dt:
10/09/2001
Publication #:
US20030070046
Pub Dt:
04/10/2003
Title:
METHOD AND APPARATUS FOR CACHE SPACE ALLOCATION
52
Patent #:
8261022
Issue Dt:
09/04/2012
Application #:
09975764
Filing Dt:
10/09/2001
Publication #:
US20030070047
Pub Dt:
04/10/2003
Title:
METHOD AND APPARATUS FOR ADAPTIVE CACHE FRAME LOCKING AND UNLOCKING
53
Patent #:
6555914
Issue Dt:
04/29/2003
Application #:
09975871
Filing Dt:
10/12/2001
Title:
INTEGRATED CIRCUIT PACKAGE VIA
54
Patent #:
6990624
Issue Dt:
01/24/2006
Application #:
09976729
Filing Dt:
10/12/2001
Publication #:
US20030106014
Pub Dt:
06/05/2003
Title:
HIGH SPEED SYNDROME-BASED FEC ENCODER AND DECODER AND SYSTEM USING SAME
55
Patent #:
6856183
Issue Dt:
02/15/2005
Application #:
09976854
Filing Dt:
10/12/2001
Publication #:
US20030072099
Pub Dt:
04/17/2003
Title:
SCHEME TO IMPROVE PERFORMANCE OF TIMING RECOVERY SYSTEMS FOR READ CHANNELS IN A DISK DRIVE
56
Patent #:
7206369
Issue Dt:
04/17/2007
Application #:
09977045
Filing Dt:
10/12/2001
Publication #:
US20030072400
Pub Dt:
04/17/2003
Title:
PROGRAMMABLE FEEDBACK DELAY PHASE-LOCKED LOOP FOR HIGH-SPEED INPUT/OUTPUT TIMING BUDGET MANAGEMENT AND METHOD OF OPERATION THEREOF
57
Patent #:
6931606
Issue Dt:
08/16/2005
Application #:
09978141
Filing Dt:
10/15/2001
Title:
AUTOMATIC METHOD AND SYSTEM FOR INSTANTIATING BUILT-IN -TEST (BIST) MODULES IN ASIC MEMORY DESIGNS
58
Patent #:
6696744
Issue Dt:
02/24/2004
Application #:
09978871
Filing Dt:
10/15/2001
Publication #:
US20020037434
Pub Dt:
03/28/2002
Title:
INTEGRATED CIRCUIT HAVING A MICROMAGNETIC DEVICE AND METHOD OF MANUFACTURE THEREFOR
59
Patent #:
6586332
Issue Dt:
07/01/2003
Application #:
09981154
Filing Dt:
10/16/2001
Title:
DEEP SUBMICRON SILICIDE BLOCKING
60
Patent #:
6750668
Issue Dt:
06/15/2004
Application #:
09981200
Filing Dt:
10/17/2001
Title:
VORTEX UNIT FOR PROVIDING A DESIRED ENVIRONMENT FOR A SEMICONDUCTOR PROCESS
61
Patent #:
7010714
Issue Dt:
03/07/2006
Application #:
09981474
Filing Dt:
10/17/2001
Title:
PRESCALER ARCHITECTURE CAPABLE OF NON INTEGER DIVISION
62
Patent #:
6674331
Issue Dt:
01/06/2004
Application #:
09986669
Filing Dt:
11/09/2001
Publication #:
US20030090328
Pub Dt:
05/15/2003
Title:
METHOD AND APPARATUS FOR SIMPLIFIED TUNING OF A TWO-POINT MODULATED PLL
63
Patent #:
6594805
Issue Dt:
07/15/2003
Application #:
09986912
Filing Dt:
11/13/2001
Title:
INTEGRATED DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
64
Patent #:
7065158
Issue Dt:
06/20/2006
Application #:
09989052
Filing Dt:
11/20/2001
Publication #:
US20030152168
Pub Dt:
08/14/2003
Title:
DETECTION METHOD FOR PHASE-MODULATED SYMBOLS WITH A CORRELATOR-BANK
65
Patent #:
6904538
Issue Dt:
06/07/2005
Application #:
09989272
Filing Dt:
11/20/2001
Publication #:
US20030097601
Pub Dt:
05/22/2003
Title:
SYSTEM AND METHOD FOR DIFFERENTIAL DATA DETECTION
66
Patent #:
7020221
Issue Dt:
03/28/2006
Application #:
09989605
Filing Dt:
11/20/2001
Publication #:
US20030095612
Pub Dt:
05/22/2003
Title:
SYSTEM AND METHOD FOR AN IF-SAMPLING TRANSCEIVER
67
Patent #:
6594748
Issue Dt:
07/15/2003
Application #:
09990698
Filing Dt:
11/09/2001
Title:
METHODS AND STRUCTURE FOR PIPELINED READ RETURN CONTROL IN A SHARED RAM CONTROLLER
68
Patent #:
6513079
Issue Dt:
01/28/2003
Application #:
09991063
Filing Dt:
11/21/2001
Title:
AUTOMATIC NEXUS RESTORE
69
Patent #:
6664141
Issue Dt:
12/16/2003
Application #:
09991187
Filing Dt:
11/14/2001
Title:
METHOD OF FORMING METAL FUSES IN CMOS PROCESSES WITH COPPER INTERCONNECT
70
Patent #:
7001823
Issue Dt:
02/21/2006
Application #:
09991202
Filing Dt:
11/14/2001
Title:
SHALLOW TRENCH ISOLATION STRUCTURE WITH LOW TRENCH PARASITIC CAPACITANCE
71
Patent #:
6615326
Issue Dt:
09/02/2003
Application #:
09991238
Filing Dt:
11/09/2001
Title:
METHODS AND STRUCTURE FOR SEQUENCING OF ACTIVATION COMMANDS IN A HIGH-PERFORMANCE DDR SDRAM MEMORY CONTROLLER
72
Patent #:
6885078
Issue Dt:
04/26/2005
Application #:
09991277
Filing Dt:
11/09/2001
Publication #:
US20030092222
Pub Dt:
05/15/2003
Title:
CIRCUIT ISOLATION UTILIZING MEV IMPLANTATION
73
Patent #:
6550045
Issue Dt:
04/15/2003
Application #:
09991574
Filing Dt:
11/20/2001
Title:
CHANGING CLOCK DELAYS IN AN INTEGRATED CIRCUIT FOR SKEW OPTIMIZATION
74
Patent #:
6476737
Issue Dt:
11/05/2002
Application #:
09992041
Filing Dt:
11/16/2001
Title:
RATE 64/65 (D=0, G=11/I=10) RUN LENGTH LIMITED MODULATION CODE
75
Patent #:
7007201
Issue Dt:
02/28/2006
Application #:
09992043
Filing Dt:
11/16/2001
Title:
SHARED EMBEDDED TRACE MACROCELL
76
Patent #:
6750145
Issue Dt:
06/15/2004
Application #:
09992135
Filing Dt:
11/14/2001
Publication #:
US20020052115
Pub Dt:
05/02/2002
Title:
METHOD OF ELIMINATING AGGLOMERATE PARTICLES IN A POLISHING SLURRY
77
Patent #:
7499539
Issue Dt:
03/03/2009
Application #:
09992625
Filing Dt:
11/06/2001
Publication #:
US20020076038
Pub Dt:
06/20/2002
Title:
TELEPHONE LINE POWER SUPPLY
78
Patent #:
6788091
Issue Dt:
09/07/2004
Application #:
09993015
Filing Dt:
11/05/2001
Title:
METHOD AND APPARATUS FOR AUTOMATIC MARKING OF INTERGRATED CIRCUITS IN WAFER SCALE TESTING
79
Patent #:
6472279
Issue Dt:
10/29/2002
Application #:
09993414
Filing Dt:
11/05/2001
Title:
METHOD OF MANUFACTURING A CHANNEL STOP IMPLANT IN A SEMICONDUCTOR DEVICE
80
Patent #:
6558978
Issue Dt:
05/06/2003
Application #:
09993466
Filing Dt:
11/05/2001
Title:
CHIP-OVER-CHIP INTEGRATED CIRCUIT PACKAGE
81
Patent #:
6798298
Issue Dt:
09/28/2004
Application #:
09993588
Filing Dt:
11/16/2001
Publication #:
US20030095001
Pub Dt:
05/22/2003
Title:
BALANCING CIRCUIT, METHOD OF OPERATION THEREOF AND A CHARGE PUMP EMPLOYING THE SAME
82
Patent #:
6515611
Issue Dt:
02/04/2003
Application #:
09993846
Filing Dt:
11/06/2001
Title:
MULTISTAGE ANALOG-TO-DIGITAL CONVERTER WITH AMPLIFIER COMPONENT SWAPPING FOR IMPROVED LINEARITY
83
Patent #:
6728789
Issue Dt:
04/27/2004
Application #:
09994082
Filing Dt:
11/21/2001
Publication #:
US20020161946
Pub Dt:
10/31/2002
Title:
SYSTEM AND METHOD EMPLOYING A STATIC LOGICAL IDENTIFIER IN CONJUCTION WITH A LOOK UP TABLE TO PROVIDE ACCESS TO A TARGET
84
Patent #:
6549062
Issue Dt:
04/15/2003
Application #:
09994083
Filing Dt:
11/21/2001
Title:
METHOD AND APPARATUS FOR IMPROVING THE TOLERANCE OF INTEGRATED RESISTORS
85
Patent #:
6957279
Issue Dt:
10/18/2005
Application #:
09994090
Filing Dt:
11/16/2001
Publication #:
US20020161845
Pub Dt:
10/31/2002
Title:
SELECTABLE LOGICAL IDENTIFIER MAPPING
86
Patent #:
6966020
Issue Dt:
11/15/2005
Application #:
09994299
Filing Dt:
11/26/2001
Title:
IDENTIFYING FAULTY PROGRAMMABLE INTERCONNECT RESOURCES OF FIELD PROGRAMMABLE GATE ARRAYS
87
Patent #:
6745314
Issue Dt:
06/01/2004
Application #:
09994459
Filing Dt:
11/26/2001
Title:
CIRCULAR BUFFER CONTROL CIRCUIT AND METHOD OF OPERATION THEREOF
88
Patent #:
6687183
Issue Dt:
02/03/2004
Application #:
09994517
Filing Dt:
11/27/2001
Publication #:
US20030099128
Pub Dt:
05/29/2003
Title:
COMPILED VARIABLE INTERNAL SELF TIME MEMORY
89
Patent #:
6577170
Issue Dt:
06/10/2003
Application #:
09994541
Filing Dt:
11/27/2001
Publication #:
US20030098725
Pub Dt:
05/29/2003
Title:
CMOS TRANSCONDUCTOR WITH INCREASED DYNAMIC RANGE
90
Patent #:
6854082
Issue Dt:
02/08/2005
Application #:
09994556
Filing Dt:
11/27/2001
Title:
UNEQUAL ERROR PROTECTION REED-MULLER CODE GENERATOR AND DECODER
91
Patent #:
6671865
Issue Dt:
12/30/2003
Application #:
09994567
Filing Dt:
11/27/2001
Title:
HIGH DENSITY INPUT OUTPUT
92
Patent #:
7082177
Issue Dt:
07/25/2006
Application #:
09994847
Filing Dt:
11/28/2001
Publication #:
US20030099320
Pub Dt:
05/29/2003
Title:
METHODS AND DEVICES FOR IMPROVING THE SWITCHING TIMES OF PLLS
93
Patent #:
6775798
Issue Dt:
08/10/2004
Application #:
09996042
Filing Dt:
11/28/2001
Publication #:
US20030101393
Pub Dt:
05/29/2003
Title:
FAST SAMPLING TEST BENCH
94
Patent #:
6815342
Issue Dt:
11/09/2004
Application #:
09996118
Filing Dt:
11/27/2001
Title:
LOW RESISTANCE METAL INTERCONNECT LINES AND A PROCESS FOR FABRICATING THEM
95
Patent #:
6741522
Issue Dt:
05/25/2004
Application #:
09996122
Filing Dt:
11/27/2001
Title:
METHODS AND STRUCTURE FOR USING A HIGHER FREQUENCY CLOCK TO SHORTEN A MASTER DELAY LINE
96
Patent #:
6717539
Issue Dt:
04/06/2004
Application #:
09996209
Filing Dt:
11/28/2001
Publication #:
US20030098807
Pub Dt:
05/29/2003
Title:
DIGITAL-TO-ANALOG CONVERTER
97
Patent #:
7003712
Issue Dt:
02/21/2006
Application #:
09996661
Filing Dt:
11/29/2001
Publication #:
US20030101408
Pub Dt:
05/29/2003
Title:
APPARATUS AND METHOD FOR ADAPTIVE, MULTIMODE DECODING
98
Patent #:
6767692
Issue Dt:
07/27/2004
Application #:
09997071
Filing Dt:
11/28/2001
Title:
PROCESS FOR INHIBITING EDGE PEELING OF COATING ON SEMICONDUCTOR SUBSTRATE DURING FORMATION OF INTEGRATED CIRCUIT STRUCTURE THEREON
99
Patent #:
6745358
Issue Dt:
06/01/2004
Application #:
09997757
Filing Dt:
11/30/2001
Title:
ENHANCED FAULT COVERAGE
100
Patent #:
6760827
Issue Dt:
07/06/2004
Application #:
09997776
Filing Dt:
11/30/2001
Publication #:
US20030105935
Pub Dt:
06/05/2003
Title:
METHOD AND APPARATUS FOR ACCESSING ROM PCI MEMORY ABOVE 64 K
Assignors
1
LSI CORPORATION
Exec Dt:
05/06/2014
2
AGERE SYSTEMS LLC
Exec Dt:
05/06/2014
Assignee
1
DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
60 WALL STREET
NEW YORK, NEW YORK 10005
Correspondence name and address
LATHAM & WATKINS LLP
650 TOWN CENTER DRIVE, SUITE 2000
COSTA MESA, CA 92626

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