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Total properties:
28
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Patent #:
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Issue Dt:
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09/14/1999
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Application #:
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08788249
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Filing Dt:
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01/27/1997
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Title:
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SINGLE-CHIP MEMORY SYSTEM HAVING A REDUNDANCY JUDGING CIRCUIT
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Patent #:
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Issue Dt:
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05/04/1999
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Application #:
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08859715
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Filing Dt:
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05/21/1997
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Title:
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READ BUS CONTROLLING APPARATUS FOR SEMICONDUCTOR STORAGE DEVICE
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Patent #:
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Issue Dt:
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05/18/1999
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Application #:
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08876293
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Filing Dt:
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06/16/1997
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Title:
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REDUNDANT DECODER UTILIZING ADDRESS SIGNAL AND BURST LENGTH
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Patent #:
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Issue Dt:
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12/08/1998
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Application #:
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08884265
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Filing Dt:
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06/27/1997
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Title:
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SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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04/20/1999
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Application #:
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08890943
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Filing Dt:
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07/10/1997
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Title:
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SEMICONDUCTOR MEMORY AND A COLUMN REDUNDANCY DISCRIMINATION CIRCUIT APPLIED THEREIN
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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08903375
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Filing Dt:
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07/30/1997
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Title:
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SEMICONDUCTOR DEVICE HAVING REDUNDANT MEMORY CELL ARRAYS AND SERIALLY ACCESSING ADDRESSES
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Patent #:
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Issue Dt:
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09/29/1998
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Application #:
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08908709
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Filing Dt:
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08/08/1997
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Title:
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SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANT DECODER WITH SUBTANTIALLY CONSTANT MARGIN REGARDLESS OF POWER VOLTAGE LEVEL
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08938962
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Filing Dt:
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09/26/1997
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Title:
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SEMICONDUCTOR MEMORY HAVING REDUNDANCY CIRCUIT
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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09035267
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Filing Dt:
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03/05/1998
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Title:
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DYNAMIC RAM PROVIDED WITH A DEFECT RELIEF CIRCUIT
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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09064504
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Filing Dt:
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04/23/1998
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Title:
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SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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09084107
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Filing Dt:
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05/26/1998
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Title:
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SEMICONDUCTOR DEVICE WITH INCREASED REPLACEMENT EFFICIENCY BY REDUNDANT MEMORY CELL ARRAYS
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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09084251
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Filing Dt:
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05/26/1998
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Title:
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SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09102638
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Filing Dt:
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06/23/1998
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Title:
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MEMORY MODULE HAVING RANDOM ACCESS MEMORIES WITH DEFECTIVE ADDRESSES
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|
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Patent #:
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Issue Dt:
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02/08/2000
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Application #:
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09182514
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Filing Dt:
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10/30/1998
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Title:
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SEMICONDUCTOR MEMORY DEVICE WITH A REDUNDANT DECODER HAVING A SMALL SCALE IN CIRCUITRY
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|
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09220770
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Filing Dt:
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12/28/1998
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|
Title:
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SEMICONDUCTOR MEMORY DEVICE
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|
|
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Patent #:
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Issue Dt:
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09/19/2000
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Application #:
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09268994
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Filing Dt:
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03/16/1999
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Title:
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SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR RELIEVING DEFECTIVE MEMORY CELLS
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|
|
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Patent #:
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|
Issue Dt:
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12/23/2003
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Application #:
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09349761
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Filing Dt:
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07/09/1999
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT WITH MEMORY REDUNDANCY CIRCUIT
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|
|
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Patent #:
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Issue Dt:
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06/25/2002
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Application #:
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09376470
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Filing Dt:
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08/18/1999
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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|
|
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09385631
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Filing Dt:
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08/27/1999
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|
Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09409911
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Filing Dt:
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10/01/1999
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Title:
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SEMICONDUCTOR MEMORY DEVICE AND DATA TRANSMISSION METHOD
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09429304
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Filing Dt:
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10/28/1999
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|
Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT
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|
|
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Patent #:
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|
Issue Dt:
|
02/20/2001
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Application #:
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09445964
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Filing Dt:
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12/16/1999
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Title:
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SEMICONDUCTOR MEMORY
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|
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09457697
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Filing Dt:
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12/09/1999
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Title:
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PROGRAMMED CIRCUIT IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09457731
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Filing Dt:
|
12/10/1999
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Title:
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SEMICONDUCTOR MEMORY DEVICE HAVING A REDUNDANCY JUDGEMENT CIRCUIT
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|
|
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Patent #:
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|
Issue Dt:
|
06/18/2002
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Application #:
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09716252
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Filing Dt:
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11/21/2000
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|
Title:
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SEMICONDUCTOR MEMORY
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|
|
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Patent #:
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|
Issue Dt:
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03/16/2004
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Application #:
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09928497
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Filing Dt:
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08/14/2001
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Publication #:
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Pub Dt:
|
03/14/2002
| | | | |
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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|
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Patent #:
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|
Issue Dt:
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01/07/2003
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Application #:
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10067231
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Filing Dt:
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02/07/2002
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Publication #:
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Pub Dt:
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06/13/2002
| | | | |
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Title:
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SEMICONDUCTOR MEMORY
|
|
|
|
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Patent #:
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|
Issue Dt:
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02/11/2003
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Application #:
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10142897
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Filing Dt:
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05/13/2002
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Publication #:
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Pub Dt:
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09/19/2002
| | | | |
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING AN OPTIMAL CIRCUIT LAYOUT TO ENSURE STABILIZATION OF INTERNAL SOURCE VOLTAGES WITHOUT LOWERING CIRCUIT FUNCTIONS AND/OR OPERATING PERFORMANCE
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