USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	033122/0154			Pages:	8
		Recorded:	06/17/2014
Attorney Dkt #:	3521.52
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 11

Patent #:	5719070	Issue Dt:	02/17/1998	Application #:	08720852	Filing Dt:	10/02/1996
Title:	METALLIZATION COMPOSITE HAVING NICKEL INTERMEDIATE/INTERFACE

Patent #:	6770558	Issue Dt:	08/03/2004	Application #:	10371466	Filing Dt:	02/21/2003
Publication #:	US20030219970	Pub Dt:	11/27/2003
Title:	SELECTIVE FILLING OF ELECTRICALLY CONDUCTIVE VIAS FOR THREE DIMENSIONAL DEVICE STRUCTURES

Patent #:	6819566	Issue Dt:	11/16/2004	Application #:	10605752	Filing Dt:	10/23/2003
Publication #:	US20040233638	Pub Dt:	11/25/2004
Title:	IMPROVEMENTS IN GROUNDING AND THERMAL DISSIPATION FOR INTEGRATED CIRCUIT PACKAGES

Patent #:	7361581	Issue Dt:	04/22/2008	Application #:	10904677	Filing Dt:	11/23/2004
Publication #:	US20060110905	Pub Dt:	05/25/2006
Title:	HIGH SURFACE AREA ALUMINUM BOND PAD FOR THROUGH-WAFER CONNECTIONS TO AN ELECTRONIC PACKAGE

Patent #:	7485564	Issue Dt:	02/03/2009	Application #:	11673618	Filing Dt:	02/12/2007
Publication #:	US20080194095	Pub Dt:	08/14/2008
Title:	UNDERCUT-FREE BLM PROCESS FOR PB-FREE AND PB-REDUCED C4

Patent #:	7825511	Issue Dt:	11/02/2010	Application #:	12357484	Filing Dt:	01/22/2009
Publication #:	US20090127710	Pub Dt:	05/21/2009
Title:	UNDERCUT-FREE BLM PROCESS FOR PB-FREE AND PB-REDUCED C4

Patent #:	8198133	Issue Dt:	06/12/2012	Application #:	12458441	Filing Dt:	07/13/2009
Publication #:	US20110006422	Pub Dt:	01/13/2011
Title:	STRUCTURES AND METHODS TO IMPROVE LEAD-FREE C4 INTERCONNECT RELIABILITY

Patent #:	8304290	Issue Dt:	11/06/2012	Application #:	12642479	Filing Dt:	12/18/2009
Publication #:	US20110151627	Pub Dt:	06/23/2011
Title:	OVERCOMING LAMINATE WARPAGE AND MISALIGNMENT IN FLIP-CHIP PACKAGES

Patent #:	8080485	Issue Dt:	12/20/2011	Application #:	12719153	Filing Dt:	03/08/2010
Publication #:	US20100167477	Pub Dt:	07/01/2010
Title:	LOCALIZED TEMPERATURE CONTROL DURING RAPID THERMAL ANNEAL

Patent #:	8021950	Issue Dt:	09/20/2011	Application #:	12911940	Filing Dt:	10/26/2010
Title:	SEMICONDUCTOR WAFER PROCESSING METHOD THAT ALLOWS DEVICE REGIONS TO BE SELECTIVELY ANNEALED FOLLOWING BACK END OF THE LINE (BEOL) METAL WIRING LAYER FORMATION

Assignor

Exec Dt:

08/05/2013

Assignee

3050 ZANKER ROAD

SAN JOSE, CALIFORNIA 95134

Correspondence name and address
	ALLSTON L. JONES
	425 SHERMAN AVENUE, SUITE 230
	PALO ALTO, CA 94306

Search Results as of: 05/09/2024 10:41 AM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6