Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 033134/0503 | |
| Pages: | 6 |
| | Recorded: | 06/11/2014 | | |
| Attorney Dkt #: | FREESCALE RELEASE-COR |
| Conveyance: | RELEASE OF SECURITY INTEREST |
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Total properties:
7
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Patent #:
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Issue Dt:
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11/04/2008
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Application #:
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11444091
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Filing Dt:
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05/31/2006
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Publication #:
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Pub Dt:
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12/06/2007
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Title:
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METHODS AND APPARATUS FOR RF SHIELDING IN VERTICALLY-INTEGRATED SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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09/28/2010
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Application #:
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12059123
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Filing Dt:
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03/31/2008
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Publication #:
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Pub Dt:
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10/01/2009
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Title:
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SEMICONDUCTOR THROUGH SILICON VIAS OF VARIABLE SIZE AND METHOD OF FORMATION
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Patent #:
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Issue Dt:
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05/03/2011
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Application #:
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12277512
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Filing Dt:
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11/25/2008
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Publication #:
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Pub Dt:
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05/27/2010
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Title:
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THROUGH SUBSTRATE VIAS FOR BACK-SIDE INTERCONNECTIONS ON VERY THIN SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
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01/01/2013
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Application #:
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12277519
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Filing Dt:
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11/25/2008
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Publication #:
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Pub Dt:
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05/27/2010
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Title:
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3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES
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Patent #:
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Issue Dt:
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10/18/2011
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Application #:
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12748101
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Filing Dt:
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03/26/2010
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Publication #:
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Pub Dt:
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09/29/2011
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Title:
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METHOD FOR FORMING A THROUGH SILICON VIA (TSV)
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Patent #:
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Issue Dt:
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10/09/2012
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Application #:
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13043094
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Filing Dt:
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03/08/2011
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Publication #:
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Pub Dt:
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06/30/2011
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Title:
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METHODS FOR FORMING THROUGH-SUBSTRATE CONDUCTOR FILLED VIAS, AND ELECTRONIC ASSEMBLIES FORMED USING SUCH METHODS
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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13731242
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Filing Dt:
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12/31/2012
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Publication #:
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Pub Dt:
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06/06/2013
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Title:
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METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES
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Assignee
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| 6501 WILLIAM CANNON DRIVE WEST |
| AUSTIN, TEXAS 78735 |
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Correspondence name and address
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INVENSAS CORPORATION
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3025 ORCHARD PARKWAY
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ATTN: IP DEPT.
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SAN JOSE, CA 95134
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