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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	033303/0124			Pages:	80
		Recorded:	07/11/2014
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 414
Page 1 of 5
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Patent #:	6103552	Issue Dt:	08/15/2000	Application #:	09131429	Filing Dt:	08/10/1998
Title:	WAFER SCALE PACKAGING SCHEME

Patent #:	6356958	Issue Dt:	03/12/2002	Application #:	09246303	Filing Dt:	02/08/1999
Title:	INTERGRATED CIRCUIT HAS COMMON FUNCTION KNOWS GOOD INTERGRATED CIRCUIT DIE WITH MULTIPLE SELECTABLE FUNCTIONS

Patent #:	6159773	Issue Dt:	12/12/2000	Application #:	09249252	Filing Dt:	02/12/1999
Title:	STRAIN RELEASE CONTACT SYSTEM FOR INTEGRATED CIRCUITS

Patent #:	6383916	Issue Dt:	05/07/2002	Application #:	09251183	Filing Dt:	02/17/1999
Title:	TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S

Patent #:	6180426	Issue Dt:	01/30/2001	Application #:	09258911	Filing Dt:	03/01/1999
Title:	HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY

Patent #:	6555398	Issue Dt:	04/29/2003	Application #:	09422174	Filing Dt:	10/22/1999
Title:	SOFTWARE PROGRAMMABLE MULTIPLE FUNCTION INTEGRATED CIRCUIT MODULE

Patent #:	7247932	Issue Dt:	07/24/2007	Application #:	09573955	Filing Dt:	05/19/2000
Title:	CHIP PACKAGE WITH CAPACITOR

Patent #:	6350705	Issue Dt:	02/26/2002	Application #:	09617012	Filing Dt:	07/14/2000
Title:	Wafer scale packaging scheme

Patent #:	6486563	Issue Dt:	11/26/2002	Application #:	09619017	Filing Dt:	07/19/2000
Title:	WAFER SCALE PACKAGING SCHEME

Patent #:	6399997	Issue Dt:	06/04/2002	Application #:	09631041	Filing Dt:	08/01/2000
Title:	High performance system-on-chip using post passivation process and glass substrates

Patent #:	6809935	Issue Dt:	10/26/2004	Application #:	09684519	Filing Dt:	10/10/2000
Title:	THERMALLY COMPLIANT PCB SUBSTRATE FOR THE APPLICATION OF CHIP SCALE PACKAGES

Patent #:	6495442	Issue Dt:	12/17/2002	Application #:	09691497	Filing Dt:	10/18/2000
Title:	POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS

Patent #:	6387801	Issue Dt:	05/14/2002	Application #:	09707295	Filing Dt:	11/07/2000
Title:	METHOD AND AN APPARATUS TO ELECTROLESS PLATE A METAL LAYER WHILE ELIMINATING THE PHOTOELECTRIC EFFECT

Patent #:	6303423	Issue Dt:	10/16/2001	Application #:	09721722	Filing Dt:	11/27/2000
Title:	METHOD FOR FORMING HIGH PERFORMANCE SYSTEM -ON-CHIP USING POST PASSIVATION PROCESS

Patent #:	6351035	Issue Dt:	02/26/2002	Application #:	09727869	Filing Dt:	12/04/2000
Publication #:	US20010000152	Pub Dt:	04/05/2001
Title:	Strain release contact system for integrated circuits

Patent #:	6303996	Issue Dt:	10/16/2001	Application #:	09729152	Filing Dt:	12/04/2000
Publication #:	US20010000013	Pub Dt:	03/15/2001
Title:	High performance sub-system design and assembly

Patent #:	6426556	Issue Dt:	07/30/2002	Application #:	09760909	Filing Dt:	01/16/2001
Publication #:	US20020105076	Pub Dt:	08/08/2002
Title:	RELIABLE METAL BUMPS ON TOP OF I/O PADS WITH TEST PROBE MARKS

Patent #:	6815324	Issue Dt:	11/09/2004	Application #:	09783384	Filing Dt:	02/15/2001
Publication #:	US20020111009	Pub Dt:	08/15/2002
Title:	RELIABLE METAL BUMPS ON TOP OF I/O PADS AFTER REMOVAL OF TEST PROBE MARKS

Patent #:	6818545	Issue Dt:	11/16/2004	Application #:	09798654	Filing Dt:	03/05/2001
Publication #:	US20020121692	Pub Dt:	09/05/2002
Title:	LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP

Patent #:	6399975	Issue Dt:	06/04/2002	Application #:	09801327	Filing Dt:	03/07/2001
Title:	WIDE BIT MEMORY USING POST PASSIVATION INTERCONNECTION SCHEME

Patent #:	7498196	Issue Dt:	03/03/2009	Application #:	09821546	Filing Dt:	03/30/2001
Publication #:	US20020140069	Pub Dt:	10/03/2002
Title:	STRUCTURE AND MANUFACTRUING METHOD OF CHIP SCALE PACKAGE

Patent #:	6586266	Issue Dt:	07/01/2003	Application #:	09849039	Filing Dt:	05/04/2001
Title:	HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY

Patent #:	6593649	Issue Dt:	07/15/2003	Application #:	09858528	Filing Dt:	05/17/2001
Title:	METHODS OF IC REROUTING OPTION FOR MULTIPLE PACKAGE SYSTEM APPLICATIONS

Patent #:	6638840	Issue Dt:	10/28/2003	Application #:	09932729	Filing Dt:	08/20/2001
Title:	ELECTRODE FOR ELECTROPLATING PLANAR STRUCTURES

Patent #:	6759275	Issue Dt:	07/06/2004	Application #:	09945436	Filing Dt:	09/04/2001
Title:	METHOD FOR MAKING HIGH-PERFORMANCE RF INTEGRATED CIRCUITS

Patent #:	6642136	Issue Dt:	11/04/2003	Application #:	09953525	Filing Dt:	09/17/2001
Title:	METHOD MAKING A LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE

Patent #:	6613606	Issue Dt:	09/02/2003	Application #:	09953544	Filing Dt:	09/17/2001
Title:	STRUCTURE OF HIGH PERFORMANCE COMBO CHIP AND PROCESSING METHOD

Patent #:	6495912	Issue Dt:	12/17/2002	Application #:	09953610	Filing Dt:	09/17/2001
Title:	STRUCTURE OF CERAMIC PACKAGE WITH INTEGRATED PASSIVE DEVICES

Patent #:	6939747	Issue Dt:	09/06/2005	Application #:	09961767	Filing Dt:	09/21/2001
Title:	MULTIPLE SELECTABLE FUNCTION INTEGRATED CIRCUIT MODULE

Patent #:	6455885	Issue Dt:	09/24/2002	Application #:	09970005	Filing Dt:	10/03/2001
Publication #:	US20020064922	Pub Dt:	05/30/2002
Title:	INDUCTOR STRUCTURE FOR HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS

Patent #:	6657310	Issue Dt:	12/02/2003	Application #:	09972639	Filing Dt:	10/09/2001
Publication #:	US20020048930	Pub Dt:	04/25/2002
Title:	TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S

Patent #:	NONE	Issue Dt:		Application #:	09997941	Filing Dt:	11/29/2001
Publication #:	US20030099907	Pub Dt:	05/29/2003
Title:	Process of rectifying a wafer thickness

Patent #:	6649509	Issue Dt:	11/18/2003	Application #:	09998862	Filing Dt:	10/24/2001
Title:	POST PASSIVATION METAL SCHEME FOR HIGH-PERFORMACNE INTEGRATED CIRCUIT DEVICES

Patent #:	6605528	Issue Dt:	08/12/2003	Application #:	10004027	Filing Dt:	10/24/2001
Title:	POST PASSIVATION METAL SCHEME FOR HIGH-PERFORMANCE INTEGRATED CIRCUIT DEVICES

Patent #:	6673698	Issue Dt:	01/06/2004	Application #:	10054001	Filing Dt:	01/19/2002
Title:	THIN FILM SEMICONDUCTOR PACKAGE UTILIZING A GLASS SUBSTRATE WITH COMOSITE POLYMER/METAL INTERCONNECT LAYERS

Patent #:	6800941	Issue Dt:	10/05/2004	Application #:	10055498	Filing Dt:	01/22/2002
Publication #:	US20030124767	Pub Dt:	07/03/2003
Title:	INTEGRATED CHIP PACKAGE STRUCTURE USING CERAMIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

Patent #:	7413929	Issue Dt:	08/19/2008	Application #:	10055499	Filing Dt:	01/22/2002
Publication #:	US20030122243	Pub Dt:	07/03/2003
Title:	INTEGRATED CHIP PACKAGE STRUCTURE USING ORGANIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

Patent #:	8119446	Issue Dt:	02/21/2012	Application #:	10055560	Filing Dt:	01/22/2002
Publication #:	US20030122244	Pub Dt:	07/03/2003
Title:	INTEGRATED CHIP PACKAGE STRUCTURE USING METAL SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

Patent #:	9030029	Issue Dt:	05/12/2015	Application #:	10055568	Filing Dt:	01/22/2002
Publication #:	US20030122246	Pub Dt:	07/03/2003
Title:	CHIP PACKAGE WITH DIE AND SUBSTRATE

Patent #:	NONE	Issue Dt:		Application #:	10055580	Filing Dt:	01/22/2002
Publication #:	US20030127734	Pub Dt:	07/10/2003
Title:	Semiconductor device with metal pillar

Patent #:	6620728	Issue Dt:	09/16/2003	Application #:	10058259	Filing Dt:	01/29/2002
Publication #:	US20020068441	Pub Dt:	06/06/2002
Title:	TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S

Patent #:	6522009	Issue Dt:	02/18/2003	Application #:	10117888	Filing Dt:	04/08/2002
Publication #:	US20020111019	Pub Dt:	08/15/2002
Title:	AN APPARATUS TO ELECTROLESS PLATE A METAL LAYER WHILE ELIMINATING THE PHOTO ELECTRIC EFFECT

Patent #:	6756295	Issue Dt:	06/29/2004	Application #:	10124388	Filing Dt:	04/15/2002
Publication #:	US20020109232	Pub Dt:	08/15/2002
Title:	CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME

Patent #:	6762115	Issue Dt:	07/13/2004	Application #:	10125226	Filing Dt:	04/16/2002
Publication #:	US20020115282	Pub Dt:	08/22/2002
Title:	CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME

Patent #:	7405149	Issue Dt:	07/29/2008	Application #:	10154662	Filing Dt:	05/24/2002
Title:	POST PASSIVATION METHOD FOR SEMICONDUCTOR CHIP OR WAFER

Patent #:	6515369	Issue Dt:	02/04/2003	Application #:	10156412	Filing Dt:	05/28/2002
Title:	HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS

Patent #:	6489656	Issue Dt:	12/03/2002	Application #:	10156589	Filing Dt:	05/28/2002
Title:	A RESISTOR FOR HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS

Patent #:	6489647	Issue Dt:	12/03/2002	Application #:	10156590	Filing Dt:	05/28/2002
Title:	A CAPACITOR FOR HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION PROCESS STRUCTURE

Patent #:	6784087	Issue Dt:	08/31/2004	Application #:	10174357	Filing Dt:	06/17/2002
Publication #:	US20030129822	Pub Dt:	07/10/2003
Title:	METHOD OF FABRICATING CYLINDRICAL BONDING STRUCTURE

Patent #:	6746898	Issue Dt:	06/08/2004	Application #:	10174462	Filing Dt:	06/17/2002
Publication #:	US20030124835	Pub Dt:	07/03/2003
Title:	INTEGRATED CHIP PACKAGE STRUCTURE USING SILICON SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

Patent #:	6734563	Issue Dt:	05/11/2004	Application #:	10278106	Filing Dt:	10/22/2002
Publication #:	US20030057531	Pub Dt:	03/27/2003
Title:	POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS

Patent #:	6806570	Issue Dt:	10/19/2004	Application #:	10279267	Filing Dt:	10/24/2002
Title:	THERMAL COMPLIANT SEMICONDUCTOR CHIP WIRING STRUCTURE FOR CHIP SCALE PACKAGING

Patent #:	6897507	Issue Dt:	05/24/2005	Application #:	10303451	Filing Dt:	11/25/2002
Publication #:	US20030071326	Pub Dt:	04/17/2003
Title:	CAPACITOR FOR HIGH PERFORMANCE SYSTEM-ON-CHIP USING POST PASSIVATION DEVICE

Patent #:	6802945	Issue Dt:	10/12/2004	Application #:	10336871	Filing Dt:	01/06/2003
Publication #:	US20040129558	Pub Dt:	07/08/2004
Title:	METHOD OF METAL SPUTTERING FOR INTEGRATED CIRCUIT METAL ROUTING

Patent #:	6798073	Issue Dt:	09/28/2004	Application #:	10337668	Filing Dt:	01/06/2003
Publication #:	US20030111711	Pub Dt:	06/19/2003
Title:	CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME

Patent #:	6700162	Issue Dt:	03/02/2004	Application #:	10337673	Filing Dt:	01/06/2003
Publication #:	US20030107136	Pub Dt:	06/12/2003
Title:	CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME

Patent #:	7045901	Issue Dt:	05/16/2006	Application #:	10371505	Filing Dt:	02/21/2003
Publication #:	US20030127749	Pub Dt:	07/10/2003
Title:	MULTIPLE CHIPS BONDED TO PACKAGING STRUCTURE WITH LOW NOISE AND MULTIPLE SELECTABLE FUNCTIONS

Patent #:	6791192	Issue Dt:	09/14/2004	Application #:	10371506	Filing Dt:	02/21/2003
Publication #:	US20030122240	Pub Dt:	07/03/2003
Title:	PRIMARY CHIPS BONDED TO A PRINTED CIRCUIT BOARD SUPPORTING A SECONDARY CHIP IN A CHIP-ON-CHIP CONNECTION

Patent #:	8211791	Issue Dt:	07/03/2012	Application #:	10382699	Filing Dt:	03/05/2003
Publication #:	US20030148604	Pub Dt:	08/07/2003
Title:	METHOD FOR FABRICATING CIRCUITRY COMPONENT

Patent #:	7360005	Issue Dt:	04/15/2008	Application #:	10385953	Filing Dt:	03/11/2003
Publication #:	US20030172364	Pub Dt:	09/11/2003
Title:	SOFTWARE PROGRAMMABLE MULTIPLE FUNCTION INTEGRATED CIRCUIT MODULE

Patent #:	6965165	Issue Dt:	11/15/2005	Application #:	10389543	Filing Dt:	03/14/2003
Publication #:	US20030170934	Pub Dt:	09/11/2003
Title:	TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S

Patent #:	7205646	Issue Dt:	04/17/2007	Application #:	10420595	Filing Dt:	04/22/2003
Publication #:	US20030205826	Pub Dt:	11/06/2003
Title:	ELECTRONIC DEVICE AND CHIP PACKAGE

Patent #:	7378735	Issue Dt:	05/27/2008	Application #:	10420596	Filing Dt:	04/22/2003
Publication #:	US20030199119	Pub Dt:	10/23/2003
Title:	HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY

Patent #:	8021976	Issue Dt:	09/20/2011	Application #:	10434142	Filing Dt:	05/08/2003
Publication #:	US20040070042	Pub Dt:	04/15/2004
Title:	METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT

Patent #:	7288845	Issue Dt:	10/30/2007	Application #:	10434524	Filing Dt:	05/08/2003
Publication #:	US20040070086	Pub Dt:	04/15/2004
Title:	FABRICATION OF WIRE BOND PADS OVER UNDERLYING ACTIVE DEVICES, PASSIVE DEVICES AND /OR DIELECTRIC LAYERS IN INTEGRATED CIRCUITS

Patent #:	7468551	Issue Dt:	12/23/2008	Application #:	10437333	Filing Dt:	05/13/2003
Publication #:	US20030201545	Pub Dt:	10/30/2003
Title:	MULTIPLE CHIPS BONDED TO PACKAGING STRUCTURE WITH LOW NOISE AND MULTIPLE SELECTABLE FUNCTIONS

Patent #:	6768208	Issue Dt:	07/27/2004	Application #:	10437355	Filing Dt:	05/13/2003
Publication #:	US20030197287	Pub Dt:	10/23/2003
Title:	MULTIPLE CHIPS BONDED TO PACKAGING STRUCTURE WITH LOW NOISE AND MULTIPLE SELECTABLE FUNCTIONS

Patent #:	8178435	Issue Dt:	05/15/2012	Application #:	10445558	Filing Dt:	05/27/2003
Publication #:	US20030222295	Pub Dt:	12/04/2003
Title:	HIGH PERFORMANCE SYSTEM-ON-CHIP INDUCTOR USING POST PASSIVATION PROCESS

Patent #:	7531417	Issue Dt:	05/12/2009	Application #:	10445559	Filing Dt:	05/27/2003
Publication #:	US20040029404	Pub Dt:	02/12/2004
Title:	HIGH PERFORMANCE SYSTEM-ON-CHIP PASSIVE DEVICE USING POST PASSIVATION PROCESS

Patent #:	6869870	Issue Dt:	03/22/2005	Application #:	10445560	Filing Dt:	05/27/2003
Publication #:	US20040016948	Pub Dt:	01/29/2004
Title:	HIGH PERFORMANCE SYSTEM-ON-CHIP DISCRETE COMPONENTS USING POST PASSIVATION PROCESS

Patent #:	8535976	Issue Dt:	09/17/2013	Application #:	10454972	Filing Dt:	06/04/2003
Publication #:	US20030205804	Pub Dt:	11/06/2003
Title:	METHOD FOR FABRICATING CHIP PACKAGE WITH DIE AND SUBSTRATE

Patent #:	6768194	Issue Dt:	07/27/2004	Application #:	10462251	Filing Dt:	06/16/2003
Publication #:	US20030211674	Pub Dt:	11/13/2003
Title:	ELECTRODE FOR ELECTROPLATING PLANAR STRUCTURES

Patent #:	7282804	Issue Dt:	10/16/2007	Application #:	10614928	Filing Dt:	07/08/2003
Publication #:	US20040023436	Pub Dt:	02/05/2004
Title:	STRUCTURE OF HIGH PERFORMANCE COMBO CHIP AND PROCESSING METHOD

Patent #:	7511376	Issue Dt:	03/31/2009	Application #:	10638018	Filing Dt:	08/08/2003
Publication #:	US20040046254	Pub Dt:	03/11/2004
Title:	CIRCUITRY COMPONENT WITH METAL LAYER OVER DIE AND EXTENDING TO PLACE NOT OVER DIE

Patent #:	6917119	Issue Dt:	07/12/2005	Application #:	10638454	Filing Dt:	08/11/2003
Publication #:	US20040032024	Pub Dt:	02/19/2004
Title:	LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE

Patent #:	7443033	Issue Dt:	10/28/2008	Application #:	10653628	Filing Dt:	09/02/2003
Publication #:	US20060038231	Pub Dt:	02/23/2006
Title:	POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS

Patent #:	7230340	Issue Dt:	06/12/2007	Application #:	10685872	Filing Dt:	10/15/2003
Publication #:	US20040089951	Pub Dt:	05/13/2004
Title:	POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS

Patent #:	6936531	Issue Dt:	08/30/2005	Application #:	10690250	Filing Dt:	10/20/2003
Publication #:	US20040079966	Pub Dt:	04/29/2004
Title:	PROCESS OF FABRICATING A CHIP STRUCTURE

Patent #:	NONE	Issue Dt:		Application #:	10690350	Filing Dt:	10/21/2003
Publication #:	US20040063249	Pub Dt:	04/01/2004
Title:	Thin film semiconductor package and method of fabrication

Patent #:	7242099	Issue Dt:	07/10/2007	Application #:	10695630	Filing Dt:	10/27/2003
Publication #:	US20040126927	Pub Dt:	07/01/2004
Title:	CHIP PACKAGE WITH MULTIPLE CHIPS CONNECTED BY BUMPS

Patent #:	8421158	Issue Dt:	04/16/2013	Application #:	10710596	Filing Dt:	07/23/2004
Publication #:	US20040245580	Pub Dt:	12/09/2004
Title:	CHIP STRUCTURE WITH A PASSIVE DEVICE AND METHOD FOR FORMING THE SAME

Patent #:	7345365	Issue Dt:	03/18/2008	Application #:	10728150	Filing Dt:	12/03/2003
Publication #:	US20040119097	Pub Dt:	06/24/2004
Title:	ELECTRONIC COMPONENT WITH DIE AND PASSIVE DEVICE

Patent #:	7394161	Issue Dt:	07/01/2008	Application #:	10730834	Filing Dt:	12/08/2003
Publication #:	US20050121804	Pub Dt:	06/09/2005
Title:	CHIP STRUCTURE WITH PADS HAVING BUMPS OR WIREBONDED WIRES FORMED THEREOVER OR USED TO BE TESTED THERETO

Patent #:	9136246	Issue Dt:	09/15/2015	Application #:	10755042	Filing Dt:	01/09/2004
Publication #:	US20040140556	Pub Dt:	07/22/2004
Title:	INTEGRATED CHIP PACKAGE STRUCTURE USING SILICON SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

Patent #:	7420276	Issue Dt:	09/02/2008	Application #:	10783195	Filing Dt:	02/20/2004
Publication #:	US20040166659	Pub Dt:	08/26/2004
Title:	POST PASSIVATION STRUCTURE FOR SEMICONDUCTOR CHIP OR WAFER

Patent #:	NONE	Issue Dt:		Application #:	10786807	Filing Dt:	02/25/2004
Publication #:	US20050186690	Pub Dt:	08/25/2005
Title:	Method for improving semiconductor wafer test accuracy

Patent #:	7297614	Issue Dt:	11/20/2007	Application #:	10794472	Filing Dt:	03/05/2004
Publication #:	US20040169264	Pub Dt:	09/02/2004
Title:	METHOD FOR FABRICATING CIRCUITRY COMPONENT

Patent #:	7470997	Issue Dt:	12/30/2008	Application #:	10796427	Filing Dt:	03/09/2004
Publication #:	US20050017361	Pub Dt:	01/27/2005
Title:	WIREBOND PAD FOR SEMICONDUCTOR CHIP OR WAFER

Patent #:	8368150	Issue Dt:	02/05/2013	Application #:	10802566	Filing Dt:	03/17/2004
Publication #:	US20040183209	Pub Dt:	09/23/2004
Title:	HIGH PERFORMANCE IC CHIP HAVING DISCRETE DECOUPLING CAPACITORS ATTACHED TO ITS IC SURFACE

Patent #:	8674507	Issue Dt:	03/18/2014	Application #:	10855086	Filing Dt:	05/27/2004
Publication #:	US20050017355	Pub Dt:	01/27/2005
Title:	WAFER LEVEL PROCESSING METHOD AND STRUCTURE TO MANUFACTURE TWO KINDS OF INTERCONNECTS, GOLD AND SOLDER, ON ONE WAFER

Patent #:	7319377	Issue Dt:	01/15/2008	Application #:	10856377	Filing Dt:	05/28/2004
Publication #:	US20040217840	Pub Dt:	11/04/2004
Title:	METHOD FOR MAKING HIGH-PERFORMANCE RF INTEGRATED CIRCUITS

Patent #:	7208834	Issue Dt:	04/24/2007	Application #:	10874704	Filing Dt:	06/22/2004
Publication #:	US20050026413	Pub Dt:	02/03/2005
Title:	BONDING STRUCTURE WITH PILLAR AND CAP

Patent #:	7265045	Issue Dt:	09/04/2007	Application #:	10925302	Filing Dt:	08/24/2004
Publication #:	US20050020052	Pub Dt:	01/27/2005
Title:	METHOD FOR FABRICATING THERMAL COMPLIANT SEMICONDUCTOR CHIP WIRING STRUCTURE FOR CHIP SCALE PACKAGING

Patent #:	NONE	Issue Dt:		Application #:	10933961	Filing Dt:	09/02/2004
Publication #:	US20050032351	Pub Dt:	02/10/2005
Title:	METHOD FOR FABRICATING CIRCUITRY COMPONENT

Patent #:	8368213	Issue Dt:	02/05/2013	Application #:	10935451	Filing Dt:	09/07/2004
Publication #:	US20050032349	Pub Dt:	02/10/2005
Title:	LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP

Patent #:	7423346	Issue Dt:	09/09/2008	Application #:	10937543	Filing Dt:	09/09/2004
Publication #:	US20060049524	Pub Dt:	03/09/2006
Title:	POST PASSIVATION INTERCONNECTION PROCESS AND STRUCTURES

Patent #:	7416971	Issue Dt:	08/26/2008	Application #:	10948020	Filing Dt:	09/23/2004
Publication #:	US20060063371	Pub Dt:	03/23/2006
Title:	TOP LAYERS OF METAL FOR INTEGRATED CIRCUITS

Patent #:	NONE	Issue Dt:		Application #:	10954781	Filing Dt:	09/30/2004
Publication #:	US20050040033	Pub Dt:	02/24/2005
Title:	METHOD OF METAL SPUTTERING FOR INTEGRATED CIRCUIT METAL ROUTING

Patent #:	7271489	Issue Dt:	09/18/2007	Application #:	10962963	Filing Dt:	10/12/2004
Title:	POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS

100

Patent #:	7465653	Issue Dt:	12/16/2008	Application #:	10962964	Filing Dt:	10/12/2004
Publication #:	US20050070085	Pub Dt:	03/31/2005
Title:	RELIABLE METAL BUMPS ON TOP OF I/O PADS AFTER REMOVAL OF TEST PROBE MARKS

Assignor

MEGIT ACQUISITION CORP.

Exec Dt:

07/09/2014

Assignee

QUALCOMM INCORPORATED

5775 MOREHOUSE DRIVE

SAN DIEGO, CALIFORNIA 92121

Correspondence name and address
	QUALCOMM INCORPORATED
	5775 MOREHOUSE DRIVE
	SAN DIEGO, CA 92121

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