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Reel/Frame:033446/0664   Pages: 8
Recorded: 08/01/2014
Attorney Dkt #:3186.0000000
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 14
1
Patent #:
Issue Dt:
12/22/1998
Application #:
08944904
Filing Dt:
10/06/1997
Title:
HIGH VOLTAGE NMOS PASS GATE FOR INTEGRATED CIRCUIT WITH HIGH VOLTAGE GENERATOR AND FLASH NON-VOLATILE MEMORY DEVICE HAVING THE PASS GATE
2
Patent #:
Issue Dt:
11/30/1999
Application #:
09159142
Filing Dt:
09/23/1998
Title:
SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
3
Patent #:
Issue Dt:
09/26/2000
Application #:
09421982
Filing Dt:
10/19/1999
Title:
SYSTEM FOR OPTIMIZING THE EQUALIZATION PULSE OF A READ SENSE AMPLIFIER FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
4
Patent #:
Issue Dt:
10/23/2001
Application #:
09724669
Filing Dt:
11/28/2000
Title:
Burst read incorporating output based redundancy
5
Patent #:
Issue Dt:
10/22/2002
Application #:
09893247
Filing Dt:
06/26/2001
Publication #:
Pub Dt:
12/13/2001
Title:
BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
6
Patent #:
Issue Dt:
12/13/2005
Application #:
10032757
Filing Dt:
12/27/2001
Title:
METHOD AND SYSTEM FOR FORMING DUAL GATE STRUCTURES IN A NONVOLATILE MEMORY USING A PROTECTIVE LAYER
7
Patent #:
Issue Dt:
10/26/2004
Application #:
10150240
Filing Dt:
05/15/2002
Title:
METHOD AND SYSTEM FOR TAILORING CORE AND PERIPHERY CELLS IN A NONVOLATILE MEMORY
8
Patent #:
Issue Dt:
01/16/2007
Application #:
10430471
Filing Dt:
05/06/2003
Title:
METHOD OF FORMATION OF GATE STACK SPACER AND CHARGE STORAGE MATERIALS HAVING REDUCED HYDROGEN CONTENT IN CHARGE TRAPPING DIELECTRIC FLASH MEMORY DEVICE
9
Patent #:
Issue Dt:
11/08/2005
Application #:
10839626
Filing Dt:
05/04/2004
Title:
MEMORY ARRAY WITH MEMORY CELLS HAVING REDUCED SHORT CHANNEL EFFECTS
10
Patent #:
Issue Dt:
12/13/2005
Application #:
10841933
Filing Dt:
05/06/2004
Title:
STRUCTURE AND METHOD FOR PROTECTING MEMORY CELLS FROM UV RADIATION DAMAGE AND UV RADIATION-INDUCED CHARGING DURING BACKEND PROCESSING
11
Patent #:
Issue Dt:
12/11/2007
Application #:
10899344
Filing Dt:
07/26/2004
Title:
THREE DIMENSIONAL POLYMER MEMORY CELL SYSTEMS
12
Patent #:
Issue Dt:
05/02/2006
Application #:
10946809
Filing Dt:
09/22/2004
Publication #:
Pub Dt:
03/23/2006
Title:
READ APPROACH FOR MULTI-LEVEL VIRTUAL GROUND MEMORY
13
Patent #:
Issue Dt:
08/19/2008
Application #:
10946812
Filing Dt:
09/22/2004
Title:
PAGE_ EXE ERASE ALGORITHM FOR FLASH MEMORY
14
Patent #:
Issue Dt:
06/27/2006
Application #:
10951410
Filing Dt:
09/28/2004
Title:
SYSTEM THAT FACILITATES READING MULTI-LEVEL DATA IN NON-VOLATILE MEMORY
Assignor
1
Exec Dt:
06/28/2004
Assignee
1
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
STERNE KESSLER GOLDSTEIN & FOX PLLC
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005

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