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Reel/Frame:034014/0846   Pages: 6
Recorded: 10/19/2014
Attorney Dkt #:040981-0072
Conveyance: CERTIFICATE OF CONVERSION
Total properties: 107
Page 1 of 2
Pages: 1 2
1
Patent #:
Issue Dt:
09/23/1997
Application #:
08513316
Filing Dt:
08/10/1995
Title:
TRANSMISSION SYSTEM FOR TRANSMITTING AND DETECTING THE BEGINNING OF THE FRAME OF A FRAME SYNCHRONIZED SIGNAL
2
Patent #:
Issue Dt:
03/13/2001
Application #:
08607730
Filing Dt:
02/27/1996
Title:
REAL-TIME HARDWARE METHOD AND APPARATUS FOR REDUCING QUEUE PROCESSING
3
Patent #:
Issue Dt:
05/18/1999
Application #:
08751045
Filing Dt:
11/15/1996
Title:
METHOD AND APPARATUS FOR CONTROLLING DATA TRANSFER RATES USING MARKING THRESHOLD IN ASYNCHRONOUS TRANSFER MODE NETWORKS
4
Patent #:
Issue Dt:
12/18/2001
Application #:
08903588
Filing Dt:
07/31/1997
Title:
MULTIPLE LINE FRAMER ENGINE
5
Patent #:
Issue Dt:
08/07/2001
Application #:
08939746
Filing Dt:
09/29/1997
Title:
IN-BAND DEVICE CONFIGURATION PROTOCOL FOR ATM TRANSMISSION CONVERGENCE DEVICES
6
Patent #:
Issue Dt:
07/17/2001
Application #:
08947538
Filing Dt:
10/11/1997
Title:
SIMPLIFIED DATA LINK PROTOCOL PROCESSOR
7
Patent #:
Issue Dt:
05/28/2002
Application #:
09182884
Filing Dt:
10/30/1998
Title:
METHOD AND APPARATUS FOR GUARANTEEING DATA TRANSFER RATES AND DELAYS IN DATA PACKET NETWORKS USING LOGARITHMIC CALENDAR QUEUES
8
Patent #:
Issue Dt:
05/09/2006
Application #:
09405205
Filing Dt:
09/24/1999
Title:
METHOD AND APPARATUS FOR INTERFACING MULTIPLE COMMUNICATION DEVICES TO A TIME DIVISION MULTIPLEXING BUS
9
Patent #:
Issue Dt:
05/17/2005
Application #:
09427961
Filing Dt:
10/27/1999
Title:
METHOD AND APPARATUS FOR INTERFACING MULTIPLE DATA CHANNELS TO A BUS
10
Patent #:
Issue Dt:
11/25/2003
Application #:
09432976
Filing Dt:
11/03/1999
Title:
SINGLE-BIT TIMESTAMPS FOR DATA TRANSFER RATE AND DELAY GUARANTEES IN A PACKET NETWORK
11
Patent #:
Issue Dt:
08/10/2004
Application #:
09459439
Filing Dt:
12/13/1999
Title:
COMMUNICATIONS SYSTEM WITH SYMMETRICAL INTERFACES AND ASSOCIATED METHODS
12
Patent #:
Issue Dt:
06/21/2005
Application #:
09459831
Filing Dt:
12/13/1999
Title:
COMMUNICATIONS SYSTEM AND ASSOCIATED METHODS WITH OUT-OF-BAND CONTROL
13
Patent #:
Issue Dt:
01/13/2004
Application #:
09459848
Filing Dt:
12/13/1999
Title:
COMMUNICATIONS SYSTEM AND ASSOCIATED DESKEWING METHODS
14
Patent #:
Issue Dt:
01/06/2004
Application #:
09460165
Filing Dt:
12/13/1999
Title:
COMMUNICATIONS SYSTEM INCLUDING LOWER RATE PARALLEL ELECTRONICS WITH SKEW COMPENSATION AND ASSOCIATED METHODS
15
Patent #:
Issue Dt:
12/27/2005
Application #:
09471806
Filing Dt:
12/23/1999
Title:
DIGITAL ADAPTIVE EQUALIZER FOR T1/E1 LONG HAUL TRANSCEIVER
16
Patent #:
Issue Dt:
04/06/2004
Application #:
09585476
Filing Dt:
06/01/2000
Title:
METHOD FOR RECONSTRUCTING AN AGGREGATE ATM CELL STREAM AND RELATED DEVICE
17
Patent #:
Issue Dt:
06/07/2005
Application #:
09587149
Filing Dt:
06/02/2000
Title:
METHOD AND APPARATUS FOR GUARANTEEING DATA TRANSFER RATES AND DELAYS IN ASYNCHRONOUS
18
Patent #:
Issue Dt:
04/11/2006
Application #:
09599250
Filing Dt:
06/22/2000
Title:
METHOD AND APPARATUS FOR PROVIDING DIFFERENTIATED QUALITY OF SERVICE GUARANTEES IN SCALABLE PACKET SWITCHES
19
Patent #:
Issue Dt:
12/05/2006
Application #:
09648996
Filing Dt:
08/28/2000
Title:
SYSTEM AND METHOD FOR REDUCING JITTER IN A PACKET TRANSPORT SYSTEM
20
Patent #:
Issue Dt:
10/26/2004
Application #:
09791139
Filing Dt:
02/22/2001
Publication #:
Pub Dt:
11/14/2002
Title:
LINK LAYER DEVICE AND METHOD OF TRANSLATING PACKETS BETWEEN TRANSPORT PROTOCOLS
21
Patent #:
Issue Dt:
10/03/2006
Application #:
09798112
Filing Dt:
03/02/2001
Title:
PROCESSOR ARCHITURE AND A METHOD OF PROCESSING
22
Patent #:
Issue Dt:
02/03/2004
Application #:
09798130
Filing Dt:
03/02/2001
Title:
PROCESSOR ARCHITECTURE AND A METHOD OF PROCESSING
23
Patent #:
Issue Dt:
02/14/2006
Application #:
09798454
Filing Dt:
03/02/2001
Publication #:
Pub Dt:
01/03/2002
Title:
FUNCTION INTERFACE SYSTEM AND METHOD OF PROCESSING ISSUED FUNCTIONS BETWEEN CO-PROCESSORS
24
Patent #:
Issue Dt:
02/01/2005
Application #:
09798472
Filing Dt:
03/02/2001
Publication #:
Pub Dt:
12/06/2001
Title:
VIRTUAL REASSEMBLY SYSTEM AND METHOD OF OPERATION THEREOF
25
Patent #:
Issue Dt:
01/17/2006
Application #:
09798479
Filing Dt:
03/02/2001
Publication #:
Pub Dt:
12/06/2001
Title:
CHECKSUM ENGINE AND A METHOD OF OPERATION THEREOF
26
Patent #:
Issue Dt:
07/12/2005
Application #:
09821893
Filing Dt:
03/30/2001
Publication #:
Pub Dt:
10/03/2002
Title:
EXTERNAL DEVICE TRANSMISSION SYSTEM AND A FAST PATTERN PROCESSOR EMPLOYING THE SAME
27
Patent #:
Issue Dt:
07/31/2007
Application #:
09821898
Filing Dt:
03/30/2001
Title:
EVENT EDGE SYNCHRONIZATION SYSTEM AND METHOD OF OPERATION THEREOF
28
Patent #:
Issue Dt:
03/07/2006
Application #:
09822655
Filing Dt:
03/30/2001
Title:
VIRTUAL SEGMENTATION SYSTEM AND METHOD OF OPERATION THEREOF
29
Patent #:
Issue Dt:
08/30/2005
Application #:
09873524
Filing Dt:
06/04/2001
Publication #:
Pub Dt:
03/28/2002
Title:
METHOD AND APPARATUS FOR GUARANTEEING DATA TRANSFER RATES AND ENFORCING CONFORMANCE WITH TRAFFIC PROFILES IN A PACKET NETWORK
30
Patent #:
Issue Dt:
04/11/2006
Application #:
09885777
Filing Dt:
06/20/2001
Publication #:
Pub Dt:
12/26/2002
Title:
DETECTION AND CORRECTION CIRCUIT FOR BLIND EQUALIZATION CONVERGENCE ERRORS
31
Patent #:
Issue Dt:
09/26/2006
Application #:
10025352
Filing Dt:
12/19/2001
Publication #:
Pub Dt:
06/19/2003
Title:
PROCESSOR WITH REDUCED MEMORY REQUIREMENTS FOR HIGH-SPEED ROUTING AND SWITCHING OF PACKETS
32
Patent #:
Issue Dt:
06/22/2004
Application #:
10029680
Filing Dt:
12/21/2001
Publication #:
Pub Dt:
06/26/2003
Title:
METHODS AND APPARATUS FOR FORMING LINKED LIST QUEUE USING CHUNK-BASED STRUCTURE
33
Patent #:
Issue Dt:
05/09/2006
Application #:
10029703
Filing Dt:
12/21/2001
Publication #:
Pub Dt:
06/26/2003
Title:
PROCESSOR WITH MULTIPLE-PASS NON-SEQUENTIAL PACKET CLASSIFICATION FEATURE
34
Patent #:
Issue Dt:
07/05/2005
Application #:
10029704
Filing Dt:
12/21/2001
Publication #:
Pub Dt:
06/26/2003
Title:
PROCESSOR WITH PACKET DATA FLUSHING FEATURE
35
Patent #:
Issue Dt:
07/18/2006
Application #:
10029705
Filing Dt:
12/21/2001
Publication #:
Pub Dt:
06/26/2003
Title:
METHOD AND APPARATUS FOR CLASSIFICATION OF PACKET DATA PRIOR TO STORAGE IN PROCESSOR BUFFER MEMORY
36
Patent #:
Issue Dt:
08/08/2006
Application #:
10032025
Filing Dt:
12/21/2001
Publication #:
Pub Dt:
06/26/2003
Title:
PROCESSOR WITH PACKET PROCESSING ORDER MAINTENANCE BASED ON PACKET FLOW IDENTIFIERS
37
Patent #:
Issue Dt:
10/12/2004
Application #:
10037082
Filing Dt:
12/21/2001
Publication #:
Pub Dt:
06/26/2003
Title:
METHOD AND APPARATUS FOR REASSEMBLY OF DATA BLOCKS WITHIN A NETWORK PROCESSOR
38
Patent #:
Issue Dt:
10/05/2004
Application #:
10037163
Filing Dt:
12/21/2001
Publication #:
Pub Dt:
06/26/2003
Title:
METHOD AND APPARATUS FOR BUFFER PARTITIONING WITHOUT LOSS OF DATA
39
Patent #:
Issue Dt:
12/25/2007
Application #:
10037165
Filing Dt:
12/21/2001
Publication #:
Pub Dt:
06/26/2003
Title:
METHOD AND APPARATUS FOR SWITCHING BETWEEN ACTIVE AND STANDBY SWITCH FABRICS WITH NO LOSS OF DATA
40
Patent #:
Issue Dt:
04/01/2008
Application #:
10081308
Filing Dt:
02/20/2002
Publication #:
Pub Dt:
08/21/2003
Title:
METHOD AND APPARATUS FOR ESTABLISHING A BOUND ON THE EFFECT OF TASK INTERFERENCE IN A CACHE MEMORY
41
Patent #:
Issue Dt:
04/29/2008
Application #:
10082776
Filing Dt:
02/25/2002
Publication #:
Pub Dt:
08/28/2003
Title:
CONTEXT SWITCHING SYSTEM FOR A MULTI-THREAD EXECUTION PIPELINE LOOP AND METHOD OF OPERATION THEREOF
42
Patent #:
Issue Dt:
10/28/2008
Application #:
10085219
Filing Dt:
02/28/2002
Publication #:
Pub Dt:
08/28/2003
Title:
PROCESSOR WITH DYNAMIC TABLE-BASED SCHEDULING USING LINKED TRANSMISSION ELEMENTS FOR HANDLING TRANSMISSION REQUEST COLLISIONS
43
Patent #:
Issue Dt:
07/17/2007
Application #:
10085222
Filing Dt:
02/28/2002
Publication #:
Pub Dt:
08/28/2003
Title:
PROCESSOR WITH TABLE-BASED SCHEDULING USING SOFTWARE-CONTROLLED INTERVAL COMPUTATION
44
Patent #:
Issue Dt:
05/29/2007
Application #:
10085223
Filing Dt:
02/28/2002
Publication #:
Pub Dt:
08/28/2003
Title:
PROCESSOR WITH DYNAMIC TABLE-BASED SCHEDULING USING MULTI-ENTRY TABLE LOCATIONS FOR HANDLING TRANSMISSION REQUEST COLLISIONS
45
Patent #:
Issue Dt:
05/08/2007
Application #:
10085771
Filing Dt:
02/28/2002
Publication #:
Pub Dt:
08/28/2003
Title:
PROCESSOR WITH SOFTWARE-CONTROLLED PROGRAMMABLE SERVICE LEVELS
46
Patent #:
Issue Dt:
02/13/2007
Application #:
10131577
Filing Dt:
04/24/2002
Publication #:
Pub Dt:
02/27/2003
Title:
BUFFER MANAGEMENT FOR MERGING PACKETS OF VIRTUAL CIRCUITS
47
Patent #:
Issue Dt:
09/08/2009
Application #:
10269928
Filing Dt:
10/11/2002
Title:
STRIPING ALGORITHM FOR SWITCHING FABRIC
48
Patent #:
Issue Dt:
01/15/2008
Application #:
10270264
Filing Dt:
10/11/2002
Title:
DEFICIT-BASED STRIPING ALGORITHM
49
Patent #:
Issue Dt:
09/16/2008
Application #:
10358678
Filing Dt:
02/05/2003
Title:
BACKPRESSURE MECHANISM FOR SWITCHING FABRIC
50
Patent #:
Issue Dt:
09/29/2009
Application #:
10417013
Filing Dt:
04/16/2003
Title:
SIMPLIFIED DATA LINK PROTOCOL PROCESSOR
51
Patent #:
Issue Dt:
09/21/2010
Application #:
10420153
Filing Dt:
04/22/2003
Publication #:
Pub Dt:
10/28/2004
Title:
POINTER GENERATION METHOD AND APPARATUS FOR DELAY COMPENSATION IN VIRTUAL CONCATENATION APPLICATIONS
52
Patent #:
Issue Dt:
02/10/2009
Application #:
10420156
Filing Dt:
04/22/2003
Publication #:
Pub Dt:
10/28/2004
Title:
STALL NEED DETECTION AND ASSOCIATED STALL MECHANISM FOR DELAY COMPENSATION IN VIRTUAL CONCATENATION APPLICATIONS
53
Patent #:
Issue Dt:
08/28/2012
Application #:
10620044
Filing Dt:
07/15/2003
Publication #:
Pub Dt:
02/03/2005
Title:
EXTENSIBLE TRAFFIC GENERATOR FOR SYNTHESIS OF NETWORK DATA TRAFFIC
54
Patent #:
Issue Dt:
10/26/2010
Application #:
10620045
Filing Dt:
07/15/2003
Publication #:
Pub Dt:
01/20/2005
Title:
METHOD AND APPARATUS FOR AUTOMATIC GENERATION OF MULTIPLE INTEGRATED CIRCUIT SIMULATION CONFIGURATION
55
Patent #:
Issue Dt:
09/15/2009
Application #:
10630961
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
02/03/2005
Title:
PROCESSOR CONFIGURED FOR EFFICIENT PROCESSING OF SINGLE-CELL PROTOCOL DATA UNITS
56
Patent #:
Issue Dt:
10/30/2007
Application #:
10675716
Filing Dt:
09/30/2003
Publication #:
Pub Dt:
03/31/2005
Title:
PROCESSOR WITH INPUT DATA BLOCK DISCARD MECHANISM FOR USE IN AN OVERSUBSCRIPTION CONDITION
57
Patent #:
Issue Dt:
10/24/2006
Application #:
10675717
Filing Dt:
09/30/2003
Publication #:
Pub Dt:
04/21/2005
Title:
PROCESSOR WITH MULTIPLE LINKED LIST STORAGE FEATURE
58
Patent #:
Issue Dt:
02/10/2009
Application #:
10675718
Filing Dt:
09/30/2003
Publication #:
Pub Dt:
04/21/2005
Title:
PROCESSOR WITH CONTINUITY CHECK CACHE
59
Patent #:
Issue Dt:
06/02/2009
Application #:
10689090
Filing Dt:
10/20/2003
Publication #:
Pub Dt:
01/06/2005
Title:
TRAFFIC MANAGEMENT USING IN-BAND FLOW CONTROL AND MULTIPLE-RATE TRAFFIC SHAPING
60
Patent #:
Issue Dt:
10/02/2007
Application #:
10699037
Filing Dt:
10/31/2003
Publication #:
Pub Dt:
05/05/2005
Title:
PROCESSOR WITH SCRIPT-BASED PERFORMANCE MONITORING
61
Patent #:
Issue Dt:
08/11/2009
Application #:
10699092
Filing Dt:
10/31/2003
Publication #:
Pub Dt:
05/05/2005
Title:
INTERNAL MEMORY CONTROLLER PROVIDING CONFIGURABLE ACCESS OF PROCESSOR CLIENTS TO MEMORY INSTANCES
62
Patent #:
Issue Dt:
01/13/2009
Application #:
10722933
Filing Dt:
11/26/2003
Publication #:
Pub Dt:
05/26/2005
Title:
PROCESSOR WITH SCHEDULER ARCHITECTURE SUPPORTING MULTIPLE DISTINCT SCHEDULING ALGORITHMS
63
Patent #:
Issue Dt:
05/15/2012
Application #:
10723150
Filing Dt:
11/26/2003
Publication #:
Pub Dt:
05/26/2005
Title:
ACCESS CONTROL LIST CONSTRUCTED AS A TREE OF MATCHING TABLES
64
Patent #:
Issue Dt:
01/05/2010
Application #:
10723160
Filing Dt:
11/26/2003
Publication #:
Pub Dt:
05/26/2005
Title:
DIRECTED GRAPH APPROACH FOR CONSTRUCTING A TREE REPRESENTATION OF AN ACCESS CONTROL LIST
65
Patent #:
Issue Dt:
01/02/2007
Application #:
10744567
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
06/23/2005
Title:
LINK LAYER DEVICE WITH CONFIGURABLE ADDRESS PIN ALLOCATION
66
Patent #:
Issue Dt:
04/18/2006
Application #:
10748378
Filing Dt:
12/30/2003
Publication #:
Pub Dt:
08/05/2004
Title:
METHOD AND APPARATUS FOR GUARANTEEING DATA TRANSFER RATES AND DELAYS IN DATA PACKET NETWORKS USING GENERALIZED DISCRETE DATA TRANSFER RATE APPROACH
67
Patent #:
Issue Dt:
08/12/2008
Application #:
10768764
Filing Dt:
01/30/2004
Publication #:
Pub Dt:
08/04/2005
Title:
LINK LAYER DEVICE WITH NON-LINEAR POLLING OF MULTIPLE PHYSICAL LAYER DEVICE PORTS
68
Patent #:
Issue Dt:
06/01/2010
Application #:
10799239
Filing Dt:
03/12/2004
Publication #:
Pub Dt:
09/15/2005
Title:
PROCESSOR HAVING SPLIT TRANSMIT AND RECEIVE MEDIA ACCESS CONTROLLER WITH REDUCED COMPLEXITY INTERFACE
69
Patent #:
Issue Dt:
06/24/2008
Application #:
10895764
Filing Dt:
07/21/2004
Publication #:
Pub Dt:
01/26/2006
Title:
DIGITAL SERVICE HIERARCHY LEVEL 3 (DS3) APPLICATION DETECTION
70
Patent #:
Issue Dt:
02/03/2009
Application #:
10899078
Filing Dt:
07/27/2004
Publication #:
Pub Dt:
12/30/2004
Title:
COMMUNICATIONS SYSTEM WITH SYMMETRICAL INTERFACES AND ASSOCIATED METHODS
71
Patent #:
Issue Dt:
10/05/2010
Application #:
10903953
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/16/2006
Title:
NETWORK-BASED DATA TRANSPORT ARCHITECTURE
72
Patent #:
Issue Dt:
12/12/2006
Application #:
10993627
Filing Dt:
11/19/2004
Publication #:
Pub Dt:
04/28/2005
Title:
VIRTUAL REASSEMBLY SYSTEM AND METHOD OF OPERATION THEREOF
73
Patent #:
Issue Dt:
11/24/2009
Application #:
11095769
Filing Dt:
03/31/2005
Publication #:
Pub Dt:
10/05/2006
Title:
APPARATUS AND METHOD FOR PROCESSING CELLS IN A ATM ADAPTATION LAYER DEVICE IN A COMMUNICATIONS SYSTEM THAT EXHIBITS CELL DELAY VARIATION
74
Patent #:
Issue Dt:
05/01/2012
Application #:
11095774
Filing Dt:
03/31/2005
Publication #:
Pub Dt:
10/05/2006
Title:
APPARATUS AND METHOD FOR HANDLING LOST CELLS IN A COMMUNICATIONS SYSTEM
75
Patent #:
Issue Dt:
06/22/2010
Application #:
11140297
Filing Dt:
05/27/2005
Publication #:
Pub Dt:
11/30/2006
Title:
CONTROLLING TIMESLOT DELAY IN A DIGITAL COMMUNICATION SYSTEM
76
Patent #:
Issue Dt:
12/15/2009
Application #:
11193799
Filing Dt:
07/29/2005
Publication #:
Pub Dt:
02/01/2007
Title:
METHODS AND APPARATUS FOR MINIMIZING SEQUENCE IDENTIFIER DIFFERENCE OF SIMULTANEOUSLY TRANSMITTED CELLS
77
Patent #:
Issue Dt:
10/06/2009
Application #:
11226507
Filing Dt:
09/13/2005
Publication #:
Pub Dt:
03/15/2007
Title:
CONFIGURABLE NETWORK CONNECTION ADDRESS FORMING HARDWARE
78
Patent #:
Issue Dt:
09/25/2007
Application #:
11237274
Filing Dt:
09/28/2005
Publication #:
Pub Dt:
02/02/2006
Title:
FAST PATTERN PROCESSOR INCLUDING A FUNCTION INTERFACE SYSTEM
79
Patent #:
Issue Dt:
10/04/2011
Application #:
11263300
Filing Dt:
10/31/2005
Publication #:
Pub Dt:
05/24/2007
Title:
CIRCUITRY FOR DETERMINING NETWORK OPERATIONS IN A NETWORK DEVICE BY ADDRESSING LOOKUP TABLES WITH CONTENTS OF PROTOCOL HEADER FIELDS
80
Patent #:
Issue Dt:
03/22/2011
Application #:
11299645
Filing Dt:
12/12/2005
Publication #:
Pub Dt:
04/27/2006
Title:
VIRTUAL SEGMENTATION SYSTEM AND METHOD OF OPERATION THEREOF
81
Patent #:
Issue Dt:
04/12/2011
Application #:
11326047
Filing Dt:
01/05/2006
Publication #:
Pub Dt:
07/05/2007
Title:
METHODS AND APPARATUS FOR REORGANIZING CELLS BUFFERED AFTER TRANSMISSION
82
Patent #:
Issue Dt:
03/31/2009
Application #:
11361820
Filing Dt:
02/24/2006
Publication #:
Pub Dt:
08/30/2007
Title:
PROCESSOR WITH FLEXIBLE CLOCK CONFIGUARATION
83
Patent #:
Issue Dt:
12/20/2011
Application #:
11367747
Filing Dt:
03/03/2006
Publication #:
Pub Dt:
10/05/2006
Title:
VIRTUAL CONCATENATION OF PDH SIGNALS
84
Patent #:
Issue Dt:
10/19/2010
Application #:
11382942
Filing Dt:
05/12/2006
Publication #:
Pub Dt:
11/15/2007
Title:
Methods and apparatus for performing network operations on packets of data in response to content of particular user-specified protocol header fields
85
Patent #:
Issue Dt:
03/30/2010
Application #:
11393172
Filing Dt:
03/30/2006
Publication #:
Pub Dt:
01/03/2008
Title:
PROCESSOR WITH CONFIGURABLE ASSOCIATION BETWEEN INTERFACE SIGNAL LINES AND CLOCK DOMAINS
86
Patent #:
Issue Dt:
09/21/2010
Application #:
11395769
Filing Dt:
03/31/2006
Publication #:
Pub Dt:
10/04/2007
Title:
SWITCH-BASED NETWORK PROCESSOR
87
Patent #:
Issue Dt:
04/19/2011
Application #:
11412762
Filing Dt:
04/27/2006
Publication #:
Pub Dt:
11/29/2007
Title:
METHODS AND APPARATUS FOR UPDATING DATA STRUCTURES DURING IN-SERVICE UPGRADE OF SOFTWARE IN NETWORK PROCESSOR
88
Patent #:
Issue Dt:
09/21/2010
Application #:
11412915
Filing Dt:
04/27/2006
Publication #:
Pub Dt:
11/01/2007
Title:
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09/21/2010
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Filing Dt:
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Pub Dt:
11/01/2007
Title:
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90
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03/06/2012
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Filing Dt:
05/26/2006
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Pub Dt:
11/29/2007
Title:
LINK LAYER DEVICE WITH CLOCK PROCESSING HARDWARE RESOURCES SHARED AMONG MULTIPLE INGRESS AND EGRESS LINKS
91
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Issue Dt:
10/06/2015
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Filing Dt:
05/30/2006
Publication #:
Pub Dt:
12/06/2007
Title:
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92
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06/28/2011
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Filing Dt:
07/21/2006
Publication #:
Pub Dt:
02/14/2008
Title:
METHODS AND APPARATUS FOR PREVENTION OF EXCESSIVE CONTROL MESSAGE TRAFFIC IN A DIGITAL NETWORKING SYSTEM
93
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05/25/2010
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11461181
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Pub Dt:
01/31/2008
Title:
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94
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03/09/2010
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08/24/2006
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Pub Dt:
05/29/2008
Title:
PORT ADDRESSING METHOD AND APPARATUS FOR LINK LAYER INTERFACE
95
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08/31/2006
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03/06/2008
Title:
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96
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01/03/2008
Title:
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97
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08/25/2009
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11536191
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Pub Dt:
04/03/2008
Title:
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98
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08/16/2007
Title:
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100
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05/25/2010
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11773344
Filing Dt:
07/03/2007
Publication #:
Pub Dt:
01/17/2008
Title:
EVENT EDGE SYNCHRONIZATION SYSTEM AND METHOD OF OPERATION THEREOF
Assignor
1
Exec Dt:
07/30/2012
Assignee
1
1110 AMERICAN PARKWAY NE
ALLENTOWN, PENNSYLVANIA 18109
Correspondence name and address
LATHAM & WATKINS LLP
650 TOWN CENTER DRIVE
SUITE 2000
COSTA MESA, CA 92626

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