|
Total properties:
86
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
06836048
|
Filing Dt:
|
03/04/1986
|
|
Title:
|
FOR FORMING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/1995
|
Application #:
|
07967311
|
Filing Dt:
|
10/28/1992
|
|
Title:
|
TEST PATTERN FAULT EQUIVALENCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
08181936
|
Filing Dt:
|
01/18/1994
|
|
Title:
|
CHEMICAL VAPOR DEPOSITION TRAP WITH TAPERED INLET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/1996
|
Application #:
|
08350395
|
Filing Dt:
|
12/05/1994
|
|
Title:
|
AN ELECTRICAL INTERCONNECT AND METHOD FOR FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/1997
|
Application #:
|
08390210
|
Filing Dt:
|
02/16/1995
|
|
Title:
|
LOGIC GATE SIZE OPTIMIZATION PROCESS FOR AN INTEGRATED CIRCUIT WHEREBY CIRCUIT SPEED IS IMPROVED WHILE CIRCUIT AREA IS OPTIMIZED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/1996
|
Application #:
|
08400686
|
Filing Dt:
|
03/08/1995
|
|
Title:
|
DIFFERENTIAL HIGH SPEED TRACK AND HOLD AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/1996
|
Application #:
|
08416236
|
Filing Dt:
|
04/04/1995
|
|
Title:
|
METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH DIAMOND HEAT DISSIPATION LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/1996
|
Application #:
|
08423614
|
Filing Dt:
|
04/17/1995
|
|
Title:
|
METHOD OF ADJUSTING A THRESHOLD VOLTAGE FOR A SEMICONDUCTOR DEVICE FABRICATED ON A SEMICONDUCTOR ON INSULATOR SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/1997
|
Application #:
|
08426211
|
Filing Dt:
|
04/21/1995
|
|
Title:
|
METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/1996
|
Application #:
|
08430105
|
Filing Dt:
|
04/27/1995
|
|
Title:
|
STRUCTURE AND METHOD FOR METALLIZATION OF SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/1996
|
Application #:
|
08435107
|
Filing Dt:
|
05/04/1995
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH IMPROVED ELECTROMIGRATION RESISTANCE AND METHOD FOR MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/1996
|
Application #:
|
08436055
|
Filing Dt:
|
05/05/1995
|
|
Title:
|
THERMOPLASTIC INTERCONNECT FOR ELECTRONIC DEVICE AND METHOD FOR MAKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/1997
|
Application #:
|
08453856
|
Filing Dt:
|
05/30/1995
|
|
Title:
|
METHOD OF MAKING A FERRITE/SEMICONDUCTOR RESONATOR/FILTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/1996
|
Application #:
|
08473833
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
PACKAGE FOR MATING WITH A SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/1998
|
Application #:
|
08499838
|
Filing Dt:
|
07/10/1995
|
|
Title:
|
METHOD FOR DESIGNING A SIGNAL DISTRIBUTION NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08512050
|
Filing Dt:
|
08/07/1995
|
|
Title:
|
METHOD FOR PRE-SHAPING A SEMICONDUCTOR SUBSTRATE FOR POLISHING AND STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1998
|
Application #:
|
08529772
|
Filing Dt:
|
09/18/1995
|
|
Title:
|
UPDATING HIERARCHICAL DAG REPRESENTATIONS THROUGH A BOTTOM UP METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/1996
|
Application #:
|
08550416
|
Filing Dt:
|
10/30/1995
|
|
Title:
|
PROCESS FOR MANUFACTURING A PACKAGE FOR MATING WITH A BARE SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/1997
|
Application #:
|
08552518
|
Filing Dt:
|
11/02/1995
|
|
Title:
|
METHOD FOR TESTING INTEGRATED DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/1996
|
Application #:
|
08557667
|
Filing Dt:
|
11/13/1995
|
|
Title:
|
LEAD FRAME ASSEMBLY FOR SURFACE MOUNT INTEGRATED CIRCUIT POWER PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/1997
|
Application #:
|
08560505
|
Filing Dt:
|
11/17/1995
|
|
Title:
|
PLANAR ENCAPSULATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08597768
|
Filing Dt:
|
02/07/1996
|
|
Title:
|
APPARATUS AND METHOD FOR AUTOMATICALLY PLACING TIES AND CONNECTION ELEMENTS WITHIN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/1998
|
Application #:
|
08625153
|
Filing Dt:
|
04/01/1996
|
|
Title:
|
METHOD AND APPARATUS FOR GENERATING INSTRUCTION/DATA STREAMS EMPLOYED TO VERIFY HARDWARE IMPLEMENTATIONS OF INTEGRATED CIRCUIT DESIGNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/1998
|
Application #:
|
08629487
|
Filing Dt:
|
04/10/1996
|
|
Title:
|
ACCURATE DELAY PREDICTION BASED ON MULTI-MODEL ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1998
|
Application #:
|
08630189
|
Filing Dt:
|
04/10/1996
|
|
Title:
|
COMPLEMENTARY NETWORK REDUCTION FOR LOAD MODELING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/1998
|
Application #:
|
08639393
|
Filing Dt:
|
04/29/1996
|
|
Title:
|
METHOD AND APPARATUS FOR INCORPORATING A MILLER COMPENSATION FOR MODELING ELECTRICAL CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/1998
|
Application #:
|
08711638
|
Filing Dt:
|
09/10/1996
|
|
Title:
|
METHOD OF SIMULATING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08740720
|
Filing Dt:
|
11/01/1996
|
|
Title:
|
AUTOMATIC SYNTHESIS OF STANDARD CELL LAYOUTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08740721
|
Filing Dt:
|
11/01/1996
|
|
Title:
|
AUTOMATIC LAYOUT STANDARD CELL ROUTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
08740768
|
Filing Dt:
|
11/01/1996
|
|
Title:
|
METHOD OF ROUTING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1999
|
Application #:
|
08753835
|
Filing Dt:
|
12/02/1996
|
|
Title:
|
METHOD FOR GENERATING A REDUCED ORDER MODEL OF AN ELECTRONIC CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/1998
|
Application #:
|
08755870
|
Filing Dt:
|
12/02/1996
|
|
Title:
|
PLATEN COATING STRUCTURE FOR CHEMICAL MECHANICAL POLISHING AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08805862
|
Filing Dt:
|
03/03/1997
|
|
Title:
|
MEHTOD FOR OPTIMIZING ELEMENT SIZES IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/1998
|
Application #:
|
08808759
|
Filing Dt:
|
03/03/1997
|
|
Title:
|
METHOD FOR DETERMINING FUNCTIONAL EQUIVALENCE BETWEEN DESIGN MODELS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1999
|
Application #:
|
08810876
|
Filing Dt:
|
03/05/1997
|
|
Title:
|
ARCHITECTURAL POWER ESTIMATION METHOD AND APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
08848907
|
Filing Dt:
|
05/01/1997
|
|
Title:
|
METHOD FOR OPTIMIZING CONTACT PIN PLACEMENT AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08887695
|
Filing Dt:
|
07/03/1997
|
|
Title:
|
METHOD OF CHEMICAL MECHANICAL POLISHING (CMP) USING AN UNDERPAD WITH DIFFERENT COMPRESSION REGIONS AND POLISHING PAD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
08888588
|
Filing Dt:
|
07/07/1997
|
|
Title:
|
METHOD FOR VERIFYING PROTOCOL CONFORMANCE OF AN ELECTRICAL INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/1998
|
Application #:
|
08974894
|
Filing Dt:
|
11/20/1997
|
|
Title:
|
METHOD OF FORMING A SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08980782
|
Filing Dt:
|
12/01/1997
|
|
Title:
|
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING CHEMICAL-MECHANICAL POLISHING HAVING A COMBINATION-STEP PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
08994389
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
METHOD OF FORMING MASK WITH ANGLED STRUTS OF REDUCED HEIGHT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
09001751
|
Filing Dt:
|
12/31/1997
|
|
Title:
|
METHOD FOR PERFORMING MODEL CHECKING IN INTEGATED CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09055510
|
Filing Dt:
|
04/06/1998
|
|
Title:
|
COPPER INTERCONNECT STRUCTURE AND METHOD OF FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09097026
|
Filing Dt:
|
06/12/1998
|
|
Title:
|
SPARSE-CARRIER DEVICES AND METHOD OF FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09216820
|
Filing Dt:
|
12/21/1998
|
|
Title:
|
PAD CONDITIONER COUPLING AND END EFFECTOR FOR A CHEMICAL MECHANICAL PLANARIZATION SYSTEM AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09274268
|
Filing Dt:
|
03/22/1999
|
|
Title:
|
SEMICONDUCTOR STRUCTURE HAVING A CRYSTALLINE ALKALINE EARTH METAL OXIDE INTERFACE WITH SILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09290385
|
Filing Dt:
|
04/12/1999
|
|
Title:
|
PROCESS OF FORMING A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09303995
|
Filing Dt:
|
05/03/1999
|
|
Title:
|
METHOD AND APPARATUS FOR INTEGRATED CIRCUIT DESIGN VERIFICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
09323256
|
Filing Dt:
|
06/01/1999
|
|
Title:
|
PROCESS FOR FORMING HIGH ASPECT RATIO CIRCUIT FEATURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09332817
|
Filing Dt:
|
06/14/1999
|
|
Title:
|
VERIFICATION OF DESIGN BLOCKS AND METHOD OF EQUIVALENCE CHECKING OF MULTIPLE DESIGN VIEWS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09352134
|
Filing Dt:
|
07/13/1999
|
|
Title:
|
METHOD FOR FORMING A DUAL INLAID COPPER INTERCONNECT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09354173
|
Filing Dt:
|
07/15/1999
|
|
Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE WITH REDUCED LEAKAGE CURRENT DENSITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09355144
|
Filing Dt:
|
07/22/1999
|
|
Title:
|
METHOD AND APPARATUS FOR CHANNEL-ROUTING OF AN ELECTRONIC DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09372860
|
Filing Dt:
|
08/12/1999
|
|
Title:
|
MODELING METHOD OF MOSFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09411725
|
Filing Dt:
|
10/01/1999
|
|
Title:
|
METHOD AND APPARATUS FOR PLACING REPEATERS IN A NETWORK OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09451552
|
Filing Dt:
|
12/01/1999
|
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT AND PLATING TOOL THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09551322
|
Filing Dt:
|
04/18/2000
|
|
Title:
|
ITERATIVE, NOISE-SENSITIVE METHOD OF ROUTING SEMICONDUCTOR NETS USING A DELAY NOISE THRESHOLD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09586189
|
Filing Dt:
|
06/02/2000
|
|
Title:
|
PAD CONDITIONER COUPLING AND END EFFECTOR FOR A CHEMICAL MECHANICAL PLANARIZATION SYSTEM AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2005
|
Application #:
|
09781492
|
Filing Dt:
|
02/13/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/15/2002
| | | | |
|
Title:
|
DESIGN ANALYSIS TOOL FOR PATH EXTRACTION AND FALSE PATH IDENTIFICATION AND METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
09885409
|
Filing Dt:
|
06/21/2001
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE INCLUDING A METAL OXIDE INTERFACE WITH SILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09896079
|
Filing Dt:
|
06/30/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/09/2003
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ANALYZING SMALL SIGNAL RESPONSE AND NOISE IN NONLINEAR CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
09910554
|
Filing Dt:
|
07/20/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2004
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR EXTRACTING A PORTION OF DATA IN A SOURCE REGISTER AND ARRANGING IT ON ONE SIDE OF A DESTINATION REGISTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09970284
|
Filing Dt:
|
10/03/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/04/2002
| | | | |
|
Title:
|
METHOD FOR FORMING A DUAL INLAID COPPER INTERCONNECT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
09986211
|
Filing Dt:
|
10/22/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2003
| | | | |
|
Title:
|
METHOD FOR GENERATING TRANSITION DELAY FAULT TEST PATTERNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
09989325
|
Filing Dt:
|
11/20/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2003
| | | | |
|
Title:
|
MODELING BEHAVIOR OF AN ELECTRICAL CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
10011329
|
Filing Dt:
|
11/05/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/11/2002
| | | | |
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2004
|
Application #:
|
10021756
|
Filing Dt:
|
12/13/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/19/2003
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR MEASURING A REQUIRED FEATURE OF A LAYER DURING A POLISHING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
10025289
|
Filing Dt:
|
12/19/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/19/2003
| | | | |
|
Title:
|
DESIGN VERIFICATION SYSTEM FOR AVOIDING FALSE FAILURES AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10155897
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Filing Dt:
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05/24/2002
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Publication #:
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Pub Dt:
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11/27/2003
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Title:
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METHOD AND APPARATUS TO DATA LOG AT-SPEED MARCH C+ MEMORY BIST
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10180740
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Filing Dt:
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06/26/2002
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Publication #:
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Pub Dt:
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01/01/2004
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Title:
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METHOD AND APPARATUS FOR MONITORING A POLISHING CONDITION OF A SURFACE OF A WAFER IN A POLISHING PROCESS
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Patent #:
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Issue Dt:
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08/02/2005
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Application #:
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10260251
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Filing Dt:
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09/30/2002
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Publication #:
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Pub Dt:
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04/01/2004
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Title:
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SYSTEM AND METHOD FOR CORRELATED CLOCK NETWORKS
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|
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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10304423
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Filing Dt:
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11/26/2002
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Publication #:
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Pub Dt:
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05/27/2004
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Title:
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NOISE ANALYSIS FOR AN INTEGRATED CIRCUIT MODEL
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10332111
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Filing Dt:
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10/29/2003
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Title:
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METHOD AND APPARATUS FOR CONSTRAINT GRAPH BASED LAYOUT COMPACTION FOR INTEGRATED CIRCUITS
|
|
|
|
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Patent #:
|
|
Issue Dt:
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08/02/2005
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Application #:
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10393592
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Filing Dt:
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03/21/2003
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Publication #:
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Pub Dt:
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09/23/2004
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Title:
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MEMORY MANAGEMENT IN A DATA PROCESSING SYSTEM
|
|
|
|
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Patent #:
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|
Issue Dt:
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08/02/2005
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Application #:
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10650002
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Filing Dt:
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08/27/2003
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Publication #:
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Pub Dt:
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03/03/2005
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Title:
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SEMICONDUCTOR PROCESS AND COMPOSITION FOR FORMING A BARRIER MATERIAL OVERLYING COPPER
|
|
|
|
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Patent #:
|
|
Issue Dt:
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02/28/2006
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Application #:
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10657304
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Filing Dt:
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09/08/2003
|
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Publication #:
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Pub Dt:
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04/29/2004
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Title:
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METHOD AND APPARATUS FOR DISTORTION ANALYSIS IN NONLINEAR CIRCUITS
|
|
|
|
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Patent #:
|
|
Issue Dt:
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08/23/2005
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Application #:
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10662541
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Filing Dt:
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09/15/2003
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Publication #:
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Pub Dt:
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10/07/2004
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Title:
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INTEGRATED CIRCUIT DIE HAVING A COPPER CONTACT AND METHOD THEREFOR
|
|
|
|
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Patent #:
|
|
Issue Dt:
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05/17/2005
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Application #:
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10672959
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Filing Dt:
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09/26/2003
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Publication #:
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Pub Dt:
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03/31/2005
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Title:
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ACCELERATED LIFE TEST OF MRAM CELLS
|
|
|
|
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Patent #:
|
|
Issue Dt:
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08/23/2005
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Application #:
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10694146
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
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04/28/2005
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Title:
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ELECTROMAGNETIC NOISE SHIELDING IN SEMICONDUCTOR PACKAGES USING CAGED INTERCONNECT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
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Application #:
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10728622
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Filing Dt:
|
12/05/2003
|
|
Publication #:
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|
Pub Dt:
|
06/09/2005
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Title:
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DERIVATION OF CIRCUIT BLOCK CONSTRAINTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
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Application #:
|
10764110
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Filing Dt:
|
01/23/2004
|
|
Title:
|
REAL-TIME DEBUG SUPPORT FOR A DMA DEVICE AND METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
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Application #:
|
10851347
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Filing Dt:
|
05/21/2004
|
|
Publication #:
|
|
Pub Dt:
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11/24/2005
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Title:
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METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE USING SILICON GERMANIUM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
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Application #:
|
10994720
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Filing Dt:
|
11/22/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
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|
Title:
|
CONTROLLED ELECTROLESS PLATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11067257
|
Filing Dt:
|
02/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
|
Title:
|
METHOD OF MAKING A NITRIDED GATE DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11099889
|
Filing Dt:
|
04/06/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
|
Title:
|
REAL-TIME DEBUG SUPPORT FOR A DMA DEVICE AND METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
11610768
|
Filing Dt:
|
12/14/2006
|
|
Publication #:
|
|
Pub Dt:
|
04/19/2007
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|
Title:
|
CONTROLLED ELECTROLESS PLATING
|
|
