Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 034120/0820 | |
| Pages: | 7 |
| | Recorded: | 11/06/2014 | | |
| Attorney Dkt #: | 0084567-885US0 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2016
|
Application #:
|
14320103
|
Filing Dt:
|
06/30/2014
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2015
| | | | |
|
Title:
|
NAND Flash Memory Integrated Circuits and Processes with Controlled Gate Height
|
|
|
Assignee
|
|
|
|
|
| TWO LEGACY TOWN CENTER, 6900 NORTH DALLAS PARKWAY |
| PLANO, TEXAS 75024 |
|
|
Correspondence name and address
|
| |
DAVIS WRIGHT TREMAINE LLP
|
| |
1201 THIRD AVENUE, SUITE 2200
|
| |
SEATTLE, WA 98101
|
Search Results as of:
05/02/2024 10:34 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
