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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:034689/0296   Pages: 36
Recorded: 12/22/2014
Conveyance: CORRECTIVE ASSIGNMENT TO ENCLUDE THE SCHEDULES FULL LIST. PREVIOUSLY RECORDED ON RELL 019069 FRAME 0318. ASSIGNOR(S) HEREBY CONFIRMS THE SCHEDULE.
Total properties: 35
1
Patent #:
6284600
Issue Dt:
09/04/2001
Application #:
09609468
Filing Dt:
07/03/2000
Title:
Species implantation for minimizing interface defect density in flash memory devices
2
Patent #:
6560729
Issue Dt:
05/06/2003
Application #:
09609793
Filing Dt:
07/03/2000
Title:
AUTOMATED DETERMINATION AND DISPLAY OF THE PHYSICAL LOCATION OF A FAILED CELL IN AN ARRAY OF MEMORY CELLS
3
Patent #:
6403420
Issue Dt:
06/11/2002
Application #:
09627664
Filing Dt:
07/28/2000
Title:
Nitrogen implant after bit-line formation for ono flash memory devices
4
Patent #:
6407960
Issue Dt:
06/18/2002
Application #:
09654831
Filing Dt:
09/01/2000
Title:
ARRANGEMENT FOR PROGRAMMING SELECTED DEVICE REGISTERS DURING INITIALIZATION FROM AN EXTERNAL MEMORY
5
Patent #:
6399998
Issue Dt:
06/04/2002
Application #:
09675401
Filing Dt:
09/29/2000
Title:
HIGH VOLTAGE INSULATED-GATE BIPOLAR SWITCH
6
Patent #:
6252803
Issue Dt:
06/26/2001
Application #:
09692881
Filing Dt:
10/23/2000
Title:
Automatic program disturb with intelligent soft programming for flash cells
7
Patent #:
6363014
Issue Dt:
03/26/2002
Application #:
09694688
Filing Dt:
10/23/2000
Title:
Low column leakage NOR flash array - single cell implementation
8
Patent #:
6524914
Issue Dt:
02/25/2003
Application #:
09699972
Filing Dt:
10/30/2000
Title:
SOURCE SIDE BORON IMPLANTING AND DIFFUSING DEVICE ARCHITECTURE FOR DEEP SUB 0.18 MICRON FLASH MEMORY
9
Patent #:
6331951
Issue Dt:
12/18/2001
Application #:
09717550
Filing Dt:
11/21/2000
Title:
Method and system for embedded chip erase verification
10
Patent #:
6596591
Issue Dt:
07/22/2003
Application #:
09739733
Filing Dt:
12/18/2000
Title:
METHODS TO FORM REDUCED DIMENSION BIT-LINE ISOLATION IN THE MANUFACTURE OF NON-VOLATILE MEMORY DEVICES
11
Patent #:
6344994
Issue Dt:
02/05/2002
Application #:
09795849
Filing Dt:
02/28/2001
Title:
Data retention characteristics as a result of high temperature bake
12
Patent #:
6442074
Issue Dt:
08/27/2002
Application #:
09795854
Filing Dt:
02/28/2001
Title:
TAILORED ERASE METHOD USING HIGHER PROGRAM VT AND HIGHER NEGATIVE GATE ERASE
13
Patent #:
6307784
Issue Dt:
10/23/2001
Application #:
09795856
Filing Dt:
02/28/2001
Title:
Negative gate erase
14
Patent #:
6493261
Issue Dt:
12/10/2002
Application #:
09795865
Filing Dt:
02/28/2001
Title:
SINGLE BIT ARRAY EDGES
15
Patent #:
6456533
Issue Dt:
09/24/2002
Application #:
09796282
Filing Dt:
02/28/2001
Publication #:
US20020159293
Pub Dt:
10/31/2002
Title:
HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
16
Patent #:
6459628
Issue Dt:
10/01/2002
Application #:
09824166
Filing Dt:
04/02/2001
Title:
SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
17
Patent #:
6515902
Issue Dt:
02/04/2003
Application #:
09873643
Filing Dt:
06/04/2001
Title:
METHOD AND APPARATUS FOR BOOSTING BITLINES FOR LOW VCC READ
18
Patent #:
6436778
Issue Dt:
08/20/2002
Application #:
09879738
Filing Dt:
06/12/2001
Title:
NOVEL RE-OXIDATION APPROACH TO IMPROVE PERIPHERAL GATE OXIDE INTEGRITY IN A TUNNEL NITRIDE OXIDATION PROCESS
19
Patent #:
6449188
Issue Dt:
09/10/2002
Application #:
09884565
Filing Dt:
06/19/2001
Title:
LOW COLUMN LEAKAGE NOR FLASH ARRAY-DOUBLE CELL IMPLEMENTATION
20
Patent #:
6465303
Issue Dt:
10/15/2002
Application #:
09885490
Filing Dt:
06/20/2001
Title:
METHOD OF MANUFACTURING SPACER ETCH MASK FOR SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TYPE NONVOLATILE MEMORY
21
Patent #:
6512701
Issue Dt:
01/28/2003
Application #:
09886861
Filing Dt:
06/21/2001
Title:
ERASE METHOD FOR DUAL BIT VIRTUAL GROUND FLASH
22
Patent #:
6900085
Issue Dt:
05/31/2005
Application #:
09891885
Filing Dt:
06/26/2001
Publication #:
US20020195663
Pub Dt:
12/26/2002
Title:
ESD IMPLANT FOLLOWING SPACER DEPOSITION
23
Patent #:
6424570
Issue Dt:
07/23/2002
Application #:
09892189
Filing Dt:
06/26/2001
Title:
MODULATED CHARGE PUMP WHICH USES AN ANALOG TO DIGITAL CONVERTER TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS
24
Patent #:
6645801
Issue Dt:
11/11/2003
Application #:
09968456
Filing Dt:
10/01/2001
Title:
SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
25
Patent #:
6566194
Issue Dt:
05/20/2003
Application #:
09968465
Filing Dt:
10/01/2001
Publication #:
US20030085417
Pub Dt:
05/08/2003
Title:
SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
26
Patent #:
6630384
Issue Dt:
10/07/2003
Application #:
09971483
Filing Dt:
10/05/2001
Title:
METHOD OF FABRICATING DOUBLE DENSED CORE GATES IN SONOS FLASH MEMORY
27
Patent #:
6515903
Issue Dt:
02/04/2003
Application #:
10050254
Filing Dt:
01/16/2002
Title:
NEGATIVE PUMP REGULATOR USING MOS CAPACITOR
28
Patent #:
6529412
Issue Dt:
03/04/2003
Application #:
10050257
Filing Dt:
01/16/2002
Title:
SOURCE SIDE SENSING SCHEME FOR VIRTUAL GROUND READ OF FLASH EPROM ARRAY WITH ADJACENT BIT PRECHARGE
29
Patent #:
7057949
Issue Dt:
06/06/2006
Application #:
10050342
Filing Dt:
01/16/2002
Title:
METHOD AND APPARATUS FOR PRE-CHARGING NEGATIVE PUMP MOS REGULATION CAPACITORS
30
Patent #:
6770938
Issue Dt:
08/03/2004
Application #:
10050394
Filing Dt:
01/16/2002
Title:
DIODE FABRICATION FOR ESD/EOS PROTECTION
31
Patent #:
6567303
Issue Dt:
05/20/2003
Application #:
10050483
Filing Dt:
01/16/2002
Title:
CHARGE INJECTION
32
Patent #:
6532175
Issue Dt:
03/11/2003
Application #:
10050650
Filing Dt:
01/16/2002
Title:
METHOD AND APPARATUS FOR SOFT PROGRAM VERIFICATION IN A MEMORY DEVICE
33
Patent #:
6590811
Issue Dt:
07/08/2003
Application #:
10173262
Filing Dt:
06/17/2002
Title:
HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
34
Patent #:
6549477
Issue Dt:
04/15/2003
Application #:
10223486
Filing Dt:
08/19/2002
Title:
SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
35
Patent #:
6768157
Issue Dt:
07/27/2004
Application #:
10413829
Filing Dt:
04/15/2003
Publication #:
US20030178667
Pub Dt:
09/25/2003
Title:
MEMORY DEVICE
Assignor
1
SPANSION INC.
Exec Dt:
01/31/2007
Assignee
1
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005

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