Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 034999/0928 | |
| Pages: | 7 |
| | Recorded: | 02/20/2015 | | |
| Attorney Dkt #: | 040981-0072 |
| Conveyance: | MERGER (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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10/13/1998
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Application #:
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08470945
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Filing Dt:
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06/05/1995
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Title:
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SEMICONDUCTOR DEVICE ASSEMBLY TECHNIQUES USING PREFORMED PLANAR STRUCTURES
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08909296
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Filing Dt:
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08/11/1997
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Title:
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SYSTEM AND METHOD FOR PERFORMING MOTION ESTIMATION WITH REDUCED MEMORY LOADING LATENCY
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Patent #:
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Issue Dt:
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11/13/2001
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Application #:
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09272732
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Filing Dt:
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12/14/1998
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Title:
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MEV IMPLANTATION TO FORM VERTICALLY MODULATED N+ BURIED LAYER IN AN NPN BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09375835
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Filing Dt:
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08/16/1999
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Title:
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SEMICONDUCTOR FLIP CHIP BALL GRID ARRAY PACKAGE
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Assignee
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| 1320 RIDDER PARK DRIVE |
| SAN JOSE, CALIFORNIA 95131 |
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Correspondence name and address
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LATHAM & WATKINS LLP
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650 TOWN CENTER DRIVE, SUITE 2000
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COSTA MESA, CA 92626
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