|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10151595
|
Filing Dt:
|
05/16/2002
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH HIGH CONDUCTIVITY REGION USING SHALLOW TRENCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10151669
|
Filing Dt:
|
05/20/2002
|
|
Title:
|
REDUCING TESTER CHANNELS FOR HIGH PINOUT INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10152590
|
Filing Dt:
|
05/21/2002
|
|
Title:
|
BOLTLESS CARRIER RING/CARRIER PLATE ATTACHMENT ASSEMBLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
10152747
|
Filing Dt:
|
05/21/2002
|
|
Title:
|
METHOD OF FORMING LOW RESISTANCE COMMON SOURCE LINE FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
10154089
|
Filing Dt:
|
05/23/2002
|
|
Title:
|
PROBE FOR TESTING INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2003
|
Application #:
|
10155500
|
Filing Dt:
|
05/23/2002
|
|
Title:
|
METHOD AND SYSTEM FOR PROVIDING A POLYSILICON STRINGER MONITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2004
|
Application #:
|
10158044
|
Filing Dt:
|
05/30/2002
|
|
Title:
|
NITRIDE BARRIER LAYER FOR PROTECTION OF ONO STRUCTURE FROM TOP OXIDE LOSS IN FABRICATION OF SONOS FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
10159078
|
Filing Dt:
|
05/31/2002
|
|
Title:
|
SEMICONDUCTOR ISOLATION MATERIAL DEPOSITION SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
10159323
|
Filing Dt:
|
05/31/2002
|
|
Title:
|
METHOD FOR INCREASING CORE GAIN IN FLASH MEMORY DEVICE USING STRAINED SILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
10160050
|
Filing Dt:
|
06/04/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/17/2002
| | | | |
|
Title:
|
METHOD OF DRIVING A SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
10160101
|
Filing Dt:
|
06/04/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/10/2002
| | | | |
|
Title:
|
MOS TRANSISTOR WITH RAMPED GATE OXIDE THICKNESS AND METHOD FOR MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10160442
|
Filing Dt:
|
05/31/2002
|
|
Title:
|
USB DEVICE COMMUNICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10163970
|
Filing Dt:
|
06/06/2002
|
|
Title:
|
IN SITU HARD MASK APPROACH FOR SELF-ALIGNED CONTACT ETCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10164465
|
Filing Dt:
|
06/05/2002
|
|
Title:
|
USER MODULE PARAMETER AND REGISTER CONFIGURATION BLOCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
10164895
|
Filing Dt:
|
06/07/2002
|
|
Title:
|
HIGH DENSITY DUAL BIT FLASH MEMORY CELL WITH NON PLANAR STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2003
|
Application #:
|
10165837
|
Filing Dt:
|
06/06/2002
|
|
Title:
|
HARD MASK REMOVAL PROCESS INCLUDING ISOLATION DIELECTRIC REFILL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
10172670
|
Filing Dt:
|
06/13/2002
|
|
Title:
|
METHOD AND SYSTEM FOR PROGRAMMING A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
10173262
|
Filing Dt:
|
06/17/2002
|
|
Title:
|
HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
10174550
|
Filing Dt:
|
06/18/2002
|
|
Title:
|
SHALLOW TRENCH ISOLATION FILL PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2004
|
Application #:
|
10174734
|
Filing Dt:
|
06/18/2002
|
|
Title:
|
TEST STRUCTURE TO MEASURE INTERLAYER DIELECTRIC EFFECTS AND BREAKDOWN AND DETECT METAL DEFECTS IN FLASH MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10175139
|
Filing Dt:
|
06/19/2002
|
|
Title:
|
SELF ALIGNED METAL INTERCONNECTION AND METHOD OF MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
10176594
|
Filing Dt:
|
06/21/2002
|
|
Title:
|
USE OF HIGH-K DIELECTRIC MATERIAL FOR ONO AND TUNNEL OXIDE TO IMPROVE FLOATING GATE FLASH MEMORY COUPLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
10176976
|
Filing Dt:
|
06/21/2002
|
|
Title:
|
SUBSTRATE CONFIGURABLE JTAG ID SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10177545
|
Filing Dt:
|
06/20/2002
|
|
Title:
|
METHOD FOR ISSUING VENDOR SPECIFIC REQUESTS FOR ACCESSING ASIC CONFIGURATION AND DESCRIPTOR MEMORY WHILE STILL USING A MASS STORAGE CLASS DRIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10177802
|
Filing Dt:
|
06/21/2002
|
|
Title:
|
DEVICE ENUMERATION CURRENT REDUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10177818
|
Filing Dt:
|
06/21/2002
|
|
Title:
|
ATA DEVICE ACCESS SYSTEM WITH SURROGATE REGISTERS CORRESPONDING TO ATA REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
10178144
|
Filing Dt:
|
06/24/2002
|
|
Title:
|
EXTRACTION OF DRAIN JUNCTION OVERLAP WITH THE GATE AND THE CHANNEL LENGTH FOR ULTRA-SMALL CMOS DEVICES WITH ULTRA-THIN GATE OXIDES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
10179723
|
Filing Dt:
|
06/25/2002
|
|
Title:
|
PROCESS TO IMPROVE THE VSS LINE FORMATION FOR HIGH DENSITY FLASH MEMORY AND RELATED STRUCTURE ASSOCIATED THEREWITH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10179813
|
Filing Dt:
|
06/24/2002
|
|
Title:
|
METHOD AND APPARATUS FOR TESTING A STORAGE INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2004
|
Application #:
|
10180695
|
Filing Dt:
|
06/26/2002
|
|
Title:
|
MAGNETIC MEMORY CELL AND METHOD FOR ASSIGNING TUNABLE WRITING CURRENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
10180772
|
Filing Dt:
|
06/25/2002
|
|
Title:
|
CHARGE GAIN/CHARGE LOSS JUNCTION LEAKAGE PREVENTION FOR FLASH TECHNOLOGY BY USING DOUBLE ISOLATION/CAPPING LAYER BETWEEN LIGHTLY DOPED DRAIN AND GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10183141
|
Filing Dt:
|
06/25/2002
|
|
Title:
|
EARLY DETECTION AND GRANT, AN ARBITRATION SCHEME FOR SINGLE TRANSFERS ON AMBA ADVANCED HIGH-PERFORMANCE BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10184232
|
Filing Dt:
|
06/28/2002
|
|
Title:
|
ASYMMETRIC DOT SHAPE FOR INCREASING SELECT-UNSELECT MARGIN IN MRAM DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10184336
|
Filing Dt:
|
06/26/2002
|
|
Title:
|
PROTECTION OF A LOW-K DIELECTRIC IN A PASSIVATION LEVEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
10184419
|
Filing Dt:
|
06/27/2002
|
|
Title:
|
METHOD TO FACILITATE TESTING OF LASER FUSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10184697
|
Filing Dt:
|
06/28/2002
|
|
Title:
|
BIPOLAR TRANSISTOR AND METHOD FOR MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10184715
|
Filing Dt:
|
06/28/2002
|
|
Title:
|
METHOD OF MANUFACTURING AN OXIDE-NITRIDE-OXIDE (ONO) DIELECTIC FOR SONOS-TYPE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2004
|
Application #:
|
10185470
|
Filing Dt:
|
06/28/2002
|
|
Title:
|
METHOD OF MANUFACTURING A DIELECTRIC LAYER FOR A SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TYPE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
10185646
|
Filing Dt:
|
06/28/2002
|
|
Title:
|
NITRIDE LAYER ON A GATE STACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2011
|
Application #:
|
10186453
|
Filing Dt:
|
06/28/2002
|
|
Title:
|
GATE STACK HAVING NITRIDE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10186465
|
Filing Dt:
|
06/28/2002
|
|
Title:
|
CONFIGURABLE USB INTERFACE WITH VIRTUAL REGISTER ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
10186466
|
Filing Dt:
|
06/28/2002
|
|
Title:
|
STOCHASTIC PULSE GENERATOR DEVICE AND METHOD OF SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
10186910
|
Filing Dt:
|
06/28/2002
|
|
Title:
|
ENABLING MULTIPLE ATA DEVICES USING A SINGLE BUS BRIDGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
10187944
|
Filing Dt:
|
07/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/05/2002
| | | | |
|
Title:
|
SERVO CONTROLLER AND SERVO CONTROL METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
10189651
|
Filing Dt:
|
07/03/2002
|
|
Title:
|
MEMORY DEVICE AND METHOD OF MAKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10190002
|
Filing Dt:
|
07/03/2002
|
|
Title:
|
METHOD FOR SEMICONDUCTOR WAFER PLANARIZATION BY ISOLATION MATERIAL GROWTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10190350
|
Filing Dt:
|
07/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2004
| | | | |
|
Title:
|
METHOD FOR PRODUCING CRYSTALLOGRAPHICALLY TEXTURED ELECTRODES FOR TEXTURED PZT CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
10190351
|
Filing Dt:
|
07/03/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2004
| | | | |
|
Title:
|
METHOD FOR PRODUCING CRYSTALLOGRAPHICALLY TEXTURED ELECTRODES FOR TEXTURED PZT CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
10190397
|
Filing Dt:
|
07/02/2002
|
|
Title:
|
METHOD FOR SEMICONDUCTOR WAFER PLANARIZATION BY CMP STOP LAYER FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10190420
|
Filing Dt:
|
07/03/2002
|
|
Title:
|
TEST STRUCTURE FOR MEASURING EFFECT OF TRENCH ISOLATION ON OXIDE IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10190916
|
Filing Dt:
|
07/08/2002
|
|
Title:
|
CHARGE PUMP CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10191546
|
Filing Dt:
|
07/10/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
|
Title:
|
METHOD OF 193 NM PHOTORESIST STABILIZATION BY THE USE OF ION IMPLANTATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
10194270
|
Filing Dt:
|
07/11/2002
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
SUBSTRATE ISOLATED TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10196106
|
Filing Dt:
|
07/15/2002
|
|
Title:
|
METHOD AND APPARATUS FOR CONFIGURING AN INTERFACE CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10197116
|
Filing Dt:
|
07/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2004
| | | | |
|
Title:
|
SYSTEM FOR USING A DYNAMIC REFERENCE IN A DOUBLE-BIT CELL MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10197152
|
Filing Dt:
|
07/15/2002
|
|
Title:
|
SYSTEM FOR RECONFIGURING A PERIPHERAL DEVICE USING CONFIGRUATION RESIDING ON THE PERIPHERAL DEVICE BY ELECTRONICALLY SIMULATING A PHYSICAL DISCONNECTION AND RECONNECTION TO A HOST DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10198418
|
Filing Dt:
|
07/17/2002
|
|
Title:
|
METHOD AND APPARATUS FOR INTERRUPT SIGNALING IN A COMMUNICATION NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10198508
|
Filing Dt:
|
07/17/2002
|
|
Title:
|
CONTROL TRANSACTION HANDLING IN A DEVICE CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
10199793
|
Filing Dt:
|
07/19/2002
|
|
Title:
|
NONVOLATILE MEMORY CELL WITH A NITRIDATED OXIDE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2003
|
Application #:
|
10200330
|
Filing Dt:
|
07/22/2002
|
|
Title:
|
ON-CHIP ERASE PULSE COUNTER FOR EFFICIENT ERASE VERIFY BIST (BUILT-IN-SELF-TEST) MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2003
|
Application #:
|
10200396
|
Filing Dt:
|
07/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
PROCESS FOR ANNEALING SEMICONDUCTORS AND/OR INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10200518
|
Filing Dt:
|
07/22/2002
|
|
Title:
|
ADDRESS SEQUENCER WITHIN BIST (BUILT-IN-SELF-TEST) SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10200526
|
Filing Dt:
|
07/22/2002
|
|
Title:
|
DIAGNOSTIC MODE FOR TESTING FUNCTIONALITY OF BIST (BUILT-IN-SELF-TEST) BACK-END STATE MACHINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
10200539
|
Filing Dt:
|
07/22/2002
|
|
Title:
|
GENERATION OF MARGINING VOLTAGE ON-CHIP DURING TESTING CAM PORTION OF FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2003
|
Application #:
|
10200544
|
Filing Dt:
|
07/22/2002
|
|
Title:
|
ON-CHIP REPAIR OF DEFECTIVE ADDRESS OF CORE FLASH MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10205414
|
Filing Dt:
|
07/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2003
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND LIQUID CRYSTAL PANEL DRIVER DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10207056
|
Filing Dt:
|
07/30/2002
|
|
Publication #:
|
|
Pub Dt:
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06/05/2003
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Title:
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SEMICONDUCTOR MEMORY AND METHOD OF DRIVING THE SAME
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10209088
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Filing Dt:
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07/30/2002
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Title:
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ARRAY OF DICE FOR TESTING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10210279
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Filing Dt:
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08/01/2002
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Title:
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INPUT GATE PROTECTION CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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10210378
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Filing Dt:
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07/31/2002
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Title:
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SYSTEM AND METHOD FOR ERASE VOLTAGE CONTROL DURING MULTIPLE SECTOR ERASE OF A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/14/2006
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Application #:
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10211317
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Filing Dt:
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08/05/2002
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Title:
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NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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10214149
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Filing Dt:
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08/08/2002
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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CURRENT PULSE RECEIVING CIRCUIT
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10215140
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Filing Dt:
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08/07/2002
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Title:
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METHOD FOR REPAIRING OVER-ERASURE OF FAST BITS IN FLOATING GATE MEMORY DEVICES
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10217403
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Filing Dt:
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08/14/2002
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Title:
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REFLOWABLE-DOPED HDP FILM
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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10217807
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Filing Dt:
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08/12/2002
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Title:
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METHOD OF PROTECTING A STACKED GATE STRUCTURE DURING FABRICATION
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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10217821
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Filing Dt:
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08/12/2002
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Title:
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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
|
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10217965
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Filing Dt:
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08/12/2002
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Title:
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METHOD AND SYSTEM FOR DETECTING TUNNEL OXIDE ENCROACHMENT ON A MEMORY DEVICE
|
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|
|
|
Patent #:
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Issue Dt:
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06/24/2008
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Application #:
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10218504
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Filing Dt:
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08/13/2002
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Title:
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METHOD AND SYSTEM FOR PROVIDING HYBRID CLOCK DISTRIBUTION
|
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Patent #:
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Issue Dt:
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03/30/2010
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Application #:
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10222155
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Filing Dt:
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08/16/2002
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Title:
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APPARATUS, SYSTEM AND METHOD FOR SHARING DATA FROM A DEVICE BETWEEN MULTIPLE COMPUTERS
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Patent #:
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Issue Dt:
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06/22/2004
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Application #:
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10223920
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Filing Dt:
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08/20/2002
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Title:
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MEMORY DEVICE AND METHOD OF MAKING
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10224737
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Filing Dt:
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08/20/2002
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Title:
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METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A GATE CURRENT MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND DEVICE THEREBY FORMED
|
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10225052
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Filing Dt:
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08/20/2002
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Title:
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METHOD OF FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE BY DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING AN OVERDRIVE CURRENT MEASUREMENT TECHNIQUE AND A DEVICE THEREBY FABRICATED
|
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Patent #:
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Issue Dt:
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03/31/2009
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Application #:
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10225658
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Filing Dt:
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08/21/2002
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Title:
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DIFFERENTIAL CRYSTAL OSCILLATOR
|
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10226778
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Filing Dt:
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08/23/2002
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Title:
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SYSTEM AND METHOD FOR DATA TRANSFORMATION OF DEVICE DATABASES FOR FORWARD COMPATIBILITY
|
|
|
|
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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10226912
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Filing Dt:
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08/22/2002
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Publication #:
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Pub Dt:
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02/26/2004
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Title:
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PRECHARGING SCHEME FOR READING A MEMORY CELL
|
|
|
|
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Patent #:
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|
Issue Dt:
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10/05/2004
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Application #:
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10228436
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Filing Dt:
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08/27/2002
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Title:
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BUFFER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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11/01/2005
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Application #:
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10229432
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Filing Dt:
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08/27/2002
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|
Title:
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DEVICE, SYSTEM AND METHOD FOR AN INTEGRATED CIRCUIT ADAPTABLE FOR USE IN COMPUTING SYSTEMS OF DIFFERING MEMORY REQUIREMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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08/31/2004
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Application #:
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10229481
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Filing Dt:
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08/28/2002
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|
Title:
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INPUT BUFFER SYSTEM USING LOW VOLTAGE TRANSISTORS
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
02/08/2005
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Application #:
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10229527
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Filing Dt:
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08/27/2002
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|
Title:
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SYSTEM AND METHOD OF ACQUIRING DELAY, SETUP AND HOLD VALUES FOR INTEGRATED CIRCUIT CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2008
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Application #:
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10230184
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Filing Dt:
|
08/27/2002
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|
Title:
|
METHOD AND SYSTEM FOR SUPPLEMENTING CURRENT DURING ENUMERATION OF A USB DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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03/16/2004
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Application #:
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10230729
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Filing Dt:
|
08/29/2002
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|
Title:
|
DUMMY WORDLINE FOR ERASE AND BITLINE LEAKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
10231551
|
Filing Dt:
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08/30/2002
|
|
Title:
|
TECHNIQUE FOR CHARACTERIZING THE PERFORMANCE OF AN OBJECT POSITIONING APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10232487
|
Filing Dt:
|
08/30/2002
|
|
Title:
|
FLOATING GATE MEMORY DEVICE WITH HOMOGENEOUS OXYNITRIDE TUNNELING DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10232586
|
Filing Dt:
|
08/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
|
Title:
|
BURIED-CHANNEL TRANSISTOR WITH REDUCED LEAKAGE CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10232920
|
Filing Dt:
|
08/30/2002
|
|
Title:
|
METHOD AND CIRCUIT FOR READING A POTENTIOMETER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
10233276
|
Filing Dt:
|
08/28/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/13/2003
| | | | |
|
Title:
|
FERROELECTRIC RANDOM ACCESS MEMORY CONFIGURABLE OUTPUT DRIVER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
10233696
|
Filing Dt:
|
09/03/2002
|
|
Title:
|
INPUT BUFFER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10233906
|
Filing Dt:
|
09/03/2002
|
|
Title:
|
FLASH MEMORY ARRAY WITH DUAL FUNCTION CONTROL LINES AND ASYMMETRICAL SOURCE AND DRAIN JUNCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10234680
|
Filing Dt:
|
09/04/2002
|
|
Title:
|
FIFO MEMORY SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
10235160
|
Filing Dt:
|
09/05/2002
|
|
Title:
|
SYSTEM AND METHOD FOR FABRICATING OPENINGS IN A SEMICONDUCTOR TOPOGRAPHY
|
|
