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06/12/2007
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10314380
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12/06/2002
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06/10/2004
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Title:
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MULTI-LAYER GATE STACK
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09/13/2005
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10314381
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12/06/2002
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Title:
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DEUTERIUM INCORPORATED NITRIDE
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05/22/2007
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10314591
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12/09/2002
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06/10/2004
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Title:
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SELF ALIGNED MEMORY ELEMENT AND WORDLINE
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02/03/2004
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10314837
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12/09/2002
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SELECTIVE FORMATION OF TOP MEMORY ELECTRODE BY ELECTROLESS FORMATION OF CONDUCTIVE MATERIALS
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12/07/2004
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10315458
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12/09/2002
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05/11/2004
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10315632
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12/10/2002
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FLASH MEMORY DEVICE HAVING FOUR-BIT CELLS
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03/21/2006
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10316569
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12/10/2002
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06/10/2004
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METHOD AND SYSTEM FOR REDUCING CONTACT DEFECTS USING NON CONVENTIONAL CONTACT FORMATION METHOD FOR SEMICONDUCTOR CELLS
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03/11/2008
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10316901
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12/12/2002
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06/26/2003
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BIPOLAR SUPPLY VOLTAGE GENERATOR AND SEMICONDUCTOR DEVICE FOR SAME
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08/24/2004
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10318543
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12/13/2002
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METHOD AND APPARATUS FOR DIFFERENTIAL SIGNAL DETECTION
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07/06/2004
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10319318
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12/13/2002
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METHOD FOR PLASMA ETCHING A MICROELECTRONIC TOPOGRAPHY USING A PULSE BIAS POWER
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02/22/2005
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10320012
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12/16/2002
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LOT-TO-LOT FEED FORWARD CMP PROCESS
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04/18/2006
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10320910
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12/17/2002
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DIFFERENTIALLY MIS-ALIGNED CONTACTS IN FLASH ARRAYS TO CALIBRATE FAILURE MODES
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10/28/2003
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10321035
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12/17/2002
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LOCALIZED MRAM DATA LINE AND METHOD OF OPERATION
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08/10/2004
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10321965
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12/17/2002
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SEMICONDUCTOR STRUCTURE HAVING ALIGNMENT MARKS WITH SHALLOW TRENCH ISOLATION
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03/22/2005
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10323002
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12/18/2002
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FABRICATION OF A BIPOLAR TRANSISTOR USING A SACRIFICIAL EMITTER
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10/18/2005
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10324308
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12/18/2002
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METHOD AND APPARATUS FOR RE-ACCESSING A FIFO LOCATION
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06/22/2004
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10324455
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12/20/2002
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PROGRAMMABLE OSCILLATOR SCHEME
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09/21/2004
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10324989
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12/20/2002
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METHOD FOR AND STRUCTURE FORMED FROM FABRICATING A RELATIVELY DEEP ISOLATION STRUCTURE
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08/14/2007
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10324990
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12/20/2002
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ENCODING VITERBI ERROR STATES INTO SINGLE CHIP SEQUENCES
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08/22/2006
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10325008
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12/20/2002
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MAGNETIC MEMORY ARRAY WITH AN IMPROVED WORD LINE CONFIGURATION
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10/07/2008
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10325011
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12/20/2002
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APPARATUS, SYSTEM, AND METHOD FOR SYNCHRONIZING SIGNALS RECEIVED BY ONE OR MORE SYSTEM COMPONENTS
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04/10/2012
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10325204
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12/18/2002
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METHOD AND SYSTEM FOR PROTECTING A WIRELESS NETWORK
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05/10/2005
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10325398
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12/18/2002
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SWITCHED CAPACITOR FILTER
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03/22/2005
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10326525
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12/20/2002
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SELF-ALIGNED CONTACT STRUCTURE WITH RAISED SOURCE AND DRAIN
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08/10/2004
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10326707
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12/20/2002
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FORMATION OF A SHALLOW TRENCH ISOLATION STRUCTURE IN INTEGRATED CIRCUITS
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07/20/2004
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10327094
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12/24/2002
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Pub Dt:
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07/10/2003
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Title:
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PULSE WIDTH DETECTION CIRCUIT FILTERING THE INPUT SIGNAL AND GENERATING A BINARY SIGNAL
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10/23/2007
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10327207
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12/20/2002
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DYNAMIC RECONFIGURATION INTERRUPT SYSTEM AND METHOD
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12/28/2004
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10327217
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12/20/2002
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06/24/2004
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SINGLE ENDED CLOCK SIGNAL GENERATOR HAVING A DIFFERENTIAL OUTPUT
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04/05/2005
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10327221
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12/20/2002
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METHOD FOR CONFIGURING CHIP SELECTS IN MEMORIES
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06/20/2006
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10327571
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12/20/2002
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REDUCING CROWBAR CURRENT IN A LATCH HYSTERESIS RECEIVER
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11/23/2004
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10328265
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12/23/2002
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METHOD OF PROTECTING FLASH MEMORY FROM DATA CORRUPTION DURING FAST POWER DOWN EVENTS
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03/06/2007
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10328904
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12/23/2002
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ANALOG SPREAD SPECTRUM SIGNAL GENERATION CIRCUIT
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11/20/2007
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10329162
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12/24/2002
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ANALOG I/O WITH DIGITAL SIGNAL PROCESSOR ARRAY
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04/04/2006
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10330589
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12/27/2002
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HIERARCHICALLY EXPANDABLE FAIR ARBITER
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06/14/2005
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10331938
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12/30/2002
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TREATMENT OF DIELECTRIC MATERIAL TO ENHANCE ETCH RATE
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02/15/2005
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10335457
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12/30/2002
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STABILITY ROBUSTNESS USING A NON-INTEGER ORDER FILTER IN A CIRCUIT
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02/20/2007
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10335925
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01/03/2003
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07/31/2003
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INTEGRATED CIRCUIT FREE FROM ACCUMULATION OF DUTY RATIO ERRORS
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06/15/2004
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10338333
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01/07/2003
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SYSTEM AND METHOD FOR CHARGE RESTORATION IN A NON-VOLATILE MEMORY DEVICE
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09/20/2005
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10339115
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01/09/2003
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CIRCUIT FOR LOCKING AN OSCILLATOR TO A DATA STREAM
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10/26/2004
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10339536
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01/08/2003
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METHOD AND SYSTEM FOR TESTING TUNNEL OXIDE ON A MEMORY-RELATED STRUCTURE
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06/06/2006
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10341424
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01/14/2003
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06/05/2003
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NONVOLATILE MEMORY DEVICE FOR STORING MULTI-BIT DATA
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04/26/2005
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10341881
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01/14/2003
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MEMORY DEVICE HAVING A P+ GATE AND THIN BOTTOM OXIDE AND METHOD OF ERASING SAME
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09/28/2004
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10342032
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01/14/2003
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FLASH MEMORY DEVICES WITH OXYNITRIDE DIELECTRIC AS THE CHARGE STORAGE MEDIA
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12/19/2006
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10342549
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01/15/2003
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DIELECTRIC MEMORY CELL STRUCTURE WITH COUNTER DOPED CHANNEL REGION
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05/17/2005
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10342585
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01/14/2003
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FLASH MEMORY CELL PROGRAMMING METHOD AND SYSTEM
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02/24/2004
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10345352
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01/16/2003
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08/14/2003
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DC-DC CONVERTER, DUTY-RATIO SETTING CIRCUIT AND ELECTRIC APPLIANCE USING THEM
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06/08/2004
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10348732
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01/21/2003
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MEMORY CIRCUIT ARRANGEMENT FOR PROGRAMMING A MEMORY CELL
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11/22/2005
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10349106
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01/23/2003
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08/07/2003
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DC OFFSET CANCEL CIRCUIT
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02/10/2004
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10349107
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01/23/2003
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08/14/2003
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DC OFFSET CANCEL CIRCUIT
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11/04/2003
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10349293
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01/21/2003
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METHOD FOR IMPROVING READ MARGIN IN A FLASH MEMORY DEVICE
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07/04/2006
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10350472
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01/23/2003
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STRUCTURE AND METHOD FOR REDUCING STANDING WAVES IN A PHOTORESIST
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07/27/2004
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10352658
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01/28/2003
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NOVEL NON-VOLATILE MEMORY CELL AND METHOD OF PROGRAMMING FOR IMPROVED DATA RETENTION
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06/20/2006
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10352943
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01/29/2003
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10/02/2003
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FINGER MOVEMENT DETECTION METHOD AND APPARATUS
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04/20/2004
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10353375
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01/29/2003
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DUAL TRISTATE PATH OUTPUT BUFFER CONTROL
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07/20/2004
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10353553
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01/29/2003
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Title:
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METHOD OF ADJUSTING THE THRESHOLD VOLTAGE OF A MOSFET
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08/03/2004
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10353558
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01/29/2003
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METHOD FOR READING A NON-VOLATILE MEMORY CELL ADJACENT TO AN INACTIVE REGION OF A NON-VOLATILE MEMORY CELL ARRAY
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02/28/2006
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10355177
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01/31/2003
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09/04/2003
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MICROCOMPUTER, METHOD OF CONTROLLING CACHE MEMORY, AND METHOD OF CONTROLLING CLOCK
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11/30/2004
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10356449
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01/31/2003
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METHOD AND DEVICE FOR GENERATING FREQUENCY ADJUSTMENT PARAMETERS FOR A VOLTAGE CONTROLLED OSCILLATOR
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10/28/2003
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10356495
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02/03/2003
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08/28/2003
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Title:
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NONVOLATILE SEMICONDUCTOR MEMORY DEVICE PROGRAMMING SECOND DYNAMIC REFERENCE CELL ACCORDING TO THRESHOLD VALUE OF FIRST DYNAMIC REFERENCE CELL
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07/20/2004
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10356496
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02/03/2003
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06/26/2003
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NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF READING OUT DATA
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05/11/2004
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10357879
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02/04/2003
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METHOD OF IMPROVING DYNAMIC REFERENCE TRACKING FOR FLASH MEMORY UNIT
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05/03/2005
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10358498
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02/04/2003
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Title:
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COMPENSATED OSCILLATOR CIRCUIT FOR CHARGE PUMPS
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04/25/2006
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10358586
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02/05/2003
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ONO FABRICATION PROCESS FOR INCREASING OXYGEN CONTENT AT BOTTOM OXIDE-SUBSTRATE INTERFACE IN FLASH MEMORY DEVICES
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09/14/2004
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10358587
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02/05/2003
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Title:
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METHODS OF CONTROLLING VSS IMPLANTS ON MEMORY DEVICES, AND SYSTEM FOR PERFORMING SAME
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08/10/2004
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10358589
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02/05/2003
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08/05/2004
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Title:
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UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING
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Issue Dt:
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10/11/2005
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10358756
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02/05/2003
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Title:
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REDUCED SILICON GOUGING AND COMMON SOURCE LINE RESISTANCE IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10358866
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Filing Dt:
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02/05/2003
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Title:
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PERFORMANCE IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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10359872
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Filing Dt:
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02/07/2003
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Title:
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METHOD OF FORMATION OF SEMICONDUCTOR RESISTANT TO HOT CARRIER INJECTION STRESS
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10360731
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Filing Dt:
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02/10/2003
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Publication #:
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Pub Dt:
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06/26/2003
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Title:
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SEMICONDUCTOR MEMORY AND OUTPUT SIGNAL CONTROL METHOD AND CIRCUIT IN SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10361378
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Filing Dt:
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02/10/2003
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Title:
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SELECTION CIRCUIT FOR ACCURATE MEMORY READ OPERATIONS
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Patent #:
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Issue Dt:
|
12/30/2003
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Application #:
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10361455
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Filing Dt:
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02/10/2003
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Title:
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METHOD FOR FABRICATING DEVICES IN CORE AND PERIPHERY SEMICONDUCTOR REGIONS USING DUAL SPACERS
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Patent #:
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Issue Dt:
|
07/27/2004
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Application #:
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10364569
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Filing Dt:
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02/10/2003
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Title:
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STRUCTURE AND METHOD FOR SUPPRESSING OXIDE ENCROACHMENT IN A FLOATING GATE MEMORY CELL
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Patent #:
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Issue Dt:
|
07/13/2004
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Application #:
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10364756
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Filing Dt:
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02/11/2003
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Publication #:
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Pub Dt:
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07/10/2003
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Title:
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PC CARD RETRACTABLE ANTENNA
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Patent #:
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Issue Dt:
|
01/06/2004
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Application #:
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10368528
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Filing Dt:
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02/18/2003
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Title:
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SONOS LATCH AND APPLICATION
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Patent #:
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Issue Dt:
|
10/10/2006
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Application #:
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10368696
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Filing Dt:
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02/19/2003
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Title:
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PROTECTION OF CHARGE TRAPPING DIELECTRIC FLASH MEMORY DEVICES FROM UV-INDUCED CHARGING IN BEOL PROCESSING
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Patent #:
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Issue Dt:
|
04/12/2005
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Application #:
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10369496
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Filing Dt:
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02/21/2003
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Publication #:
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Pub Dt:
|
01/15/2004
| | | | |
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Title:
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THRESHOLD VOLTAGE ADJUSTMENT METHOD OF NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
|
03/22/2005
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Application #:
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10373739
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Filing Dt:
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02/27/2003
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Publication #:
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Pub Dt:
|
09/25/2003
| | | | |
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Title:
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SEMICONDUCTOR DEVICE INCLUDING A VOLTAGE MONITORING CIRCUIT
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Patent #:
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Issue Dt:
|
12/21/2004
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Application #:
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10375534
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Filing Dt:
|
02/27/2003
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Title:
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SEMICONDUCTOR TOPOGRAPHY HAVING AN INACTIVE REGION FORMED FROM A DUMMY STRUCTURE PATTERN
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Patent #:
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Issue Dt:
|
06/27/2006
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Application #:
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10376056
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Filing Dt:
|
02/27/2003
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Title:
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VOLTAGE TRANSLATOR CIRCUIT FORMED USING LOW VOLTAGE TRANSISTORS
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Patent #:
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Issue Dt:
|
03/29/2005
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Application #:
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10378885
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Filing Dt:
|
03/05/2003
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Title:
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IMPLANT DAMAGE REMOVAL BY LASER THERMAL ANNEALING
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Patent #:
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|
Issue Dt:
|
05/17/2005
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Application #:
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10379744
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Filing Dt:
|
03/05/2003
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|
Title:
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FAST BANDGAP REFERENCE CIRCUIT FOR USE IN A LOW POWER SUPPLY A/D BOOSTER
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|
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Patent #:
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|
Issue Dt:
|
08/24/2004
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Application #:
|
10379885
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Filing Dt:
|
03/05/2003
|
|
Title:
|
METHOD OF PROGRAMMING A MEMORY CELL
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/21/2004
|
Application #:
|
10382726
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Filing Dt:
|
03/05/2003
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|
Publication #:
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Pub Dt:
|
09/09/2004
| | | | |
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Title:
|
CHARGE-TRAPPING MEMORY ARRAYS RESISTANT TO DAMAGE FROM CONTACT HOLE FORMATION
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|
|
|
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Patent #:
|
|
Issue Dt:
|
06/01/2004
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Application #:
|
10382731
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Filing Dt:
|
03/05/2003
|
|
Title:
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MEMORY ARRAY HAVING SHALLOW BIT LINE WITH SILICIDE CONTACT PORTION AND METHOD OF FORMATION
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|
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Patent #:
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|
Issue Dt:
|
08/24/2004
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Application #:
|
10382744
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Filing Dt:
|
03/05/2003
|
|
Title:
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METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY
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Patent #:
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|
Issue Dt:
|
01/08/2013
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Application #:
|
10383068
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Filing Dt:
|
03/07/2003
|
|
Title:
|
CONTROL SYSTEM FOR CHARGING BATTERIES AND ELECTRONIC APPARATUS USING SAME
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|
|
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|
Patent #:
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|
Issue Dt:
|
07/04/2006
|
Application #:
|
10384856
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Filing Dt:
|
03/10/2003
|
|
Title:
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METHOD AND SYSTEM FOR APPLYING TESTING VOLTAGE SIGNAL
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|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
|
Application #:
|
10384936
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Filing Dt:
|
03/10/2003
|
|
Title:
|
METHOD AND SYSTEM FOR DETECTING DEFECTIVE MATERIAL SURROUNDING FLASH MEMORY CELLS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2003
|
Application #:
|
10385375
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Filing Dt:
|
03/10/2003
|
|
Title:
|
SPIN ON POLYMERS FOR ORGANIC MEMORY DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10385527
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Filing Dt:
|
03/12/2003
|
|
Publication #:
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|
Pub Dt:
|
04/22/2004
| | | | |
|
Title:
|
INTERNAL BUS TESTING DEVICE AND METHOD
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/28/2005
|
Application #:
|
10387064
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Filing Dt:
|
03/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
|
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10387427
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Filing Dt:
|
03/14/2003
|
|
Publication #:
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|
Pub Dt:
|
10/23/2003
| | | | |
|
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME
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|
|
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|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10387617
|
Filing Dt:
|
03/13/2003
|
|
Title:
|
CIRCUIT FOR FAST AND ACCURATE MEMORY READ OPERATIONS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10387774
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Filing Dt:
|
03/12/2003
|
|
Title:
|
MEMORY DEVICE HAVING REVERSE LDD
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/16/2004
|
Application #:
|
10389149
|
Filing Dt:
|
03/13/2003
|
|
Title:
|
APPARATUS AND METHOD FOR A SENSE AMPLIFIER CIRCUIT THAT SAMPLES AND HOLDS A REFERENCE VOLTAGE
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|
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|
Patent #:
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|
Issue Dt:
|
02/15/2005
|
Application #:
|
10389276
|
Filing Dt:
|
03/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
|
Title:
|
COLUMN DECODER CONFIGURATION FOR A 1T/1C MEMORY
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|
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|
Patent #:
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|
Issue Dt:
|
07/05/2005
|
Application #:
|
10392912
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Filing Dt:
|
03/21/2003
|
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Publication #:
|
|
Pub Dt:
|
09/25/2003
| | | | |
|
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY THAT IS BASED ON A VIRTUAL GROUND METHOD
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|
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Patent #:
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|
Issue Dt:
|
07/26/2005
|
Application #:
|
10393032
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Filing Dt:
|
03/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/25/2003
| | | | |
|
Title:
|
ADJUSTMENT OF THRESHOLD VOLTAGES OF SELECTED NMOS AND PMOS TRANSISTORS USING FEWER MASKING STEPS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/23/2003
|
Application #:
|
10394565
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Filing Dt:
|
03/21/2003
|
|
Title:
|
ALIGNMENT SYSTEM FOR PLANAR CHARGE TRAPPING DIELECTRIC MEMORY CELL LITHOGRAPHY
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|
|
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|
Patent #:
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|
Issue Dt:
|
03/21/2006
|
Application #:
|
10396005
|
Filing Dt:
|
03/25/2003
|
|
Title:
|
PHASE-FREQUENCY DETECTOR AND CHARGE PUMP WITH FEEDBACK
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|
