|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
10818261
|
Filing Dt:
|
04/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
MEMORY DEVICE AND METHODS OF USING AND MAKING THE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10819162
|
Filing Dt:
|
04/07/2004
|
|
Title:
|
FLASH MEMORY DEVICE AND METHOD OF FORMING THE SAME WITH IMPROVED GATE BREAKDOWN AND ENDURANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10821312
|
Filing Dt:
|
04/08/2004
|
|
Title:
|
NARROW WIDE SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
10823529
|
Filing Dt:
|
04/13/2004
|
|
Title:
|
SOFT ERROR RESISTANT MEMORY CELL AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
10823970
|
Filing Dt:
|
04/13/2004
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A PAD METAL LAYER AND A LOWER METAL LAYER THAT ARE ELECTRICALLY COUPLED, WHEREAS APERTURES ARE FORMED IN THE LOWER METAL LAYER BELOW A CENTER AREA OF THE PAD METAL LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10823972
|
Filing Dt:
|
04/13/2004
|
|
Title:
|
MEMORY DEVICE WITH AN ALTERNATING VSS INTERCONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10824006
|
Filing Dt:
|
04/13/2004
|
|
Title:
|
METHOD AND SYSTEM FOR UNIVERSAL PACKAGING IN CONJUNCTION WITH A BACK-END INTEGRATED CIRCUIT MANUFACTURING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10827785
|
Filing Dt:
|
04/19/2004
|
|
Title:
|
CURRENT SOURCE ARCHITECTURE FOR MEMORY DEVICE STANDBY CURRENT REDUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10833357
|
Filing Dt:
|
04/28/2004
|
|
Title:
|
FAIL-SAFE ZERO DELAY BUFFER WITH AUTOMATIC INTERNAL REFERENCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10834950
|
Filing Dt:
|
04/28/2004
|
|
Title:
|
CIRCUIT AND METHOD TO ELIMINATE STARTUP AND SHUTOFF RUNT PULSES FROM CRYSTAL OSCILLATORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10835341
|
Filing Dt:
|
04/28/2004
|
|
Title:
|
METHOD FOR PROVIDING SHORT CHANNEL EFFECT CONTROL USING A SILICIDE VSS LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10838215
|
Filing Dt:
|
05/05/2004
|
|
Title:
|
FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10838791
|
Filing Dt:
|
05/03/2004
|
|
Title:
|
METHOD OF PERFORMING BACK-END MANUFACTURING OF AN INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
10838962
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
METHOD FOR MINIMIZING FALSE DETECTION OF STATES IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10839561
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
METHOD AND APPARATUS FOR ELIMINATING WORD LINE BENDING BY SOURCE SIDE IMPLANTATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10839562
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
POSITIVE GATE STRESS DURING ERASE TO IMPROVE RETENTION IN MULTI-LEVEL, NON-VOLATILE FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10839614
|
Filing Dt:
|
05/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR WORDLINE PROTECTION IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10839626
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
MEMORY ARRAY WITH MEMORY CELLS HAVING REDUCED SHORT CHANNEL EFFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
10839817
|
Filing Dt:
|
05/05/2004
|
|
Title:
|
SYSTEM, METHOD AND APPARATUS FOR EXTENDING DISTANCES BETWEEN WIRED OR WIRELESS USB DEVICES AND A USB HOST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
10839822
|
Filing Dt:
|
05/05/2004
|
|
Title:
|
BATTERY WITH ELECTRONIC COMPARTMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10841850
|
Filing Dt:
|
05/07/2004
|
|
Title:
|
FLASH MEMORY CELL AND METHODS FOR PROGRAMMING AND ERASING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10841933
|
Filing Dt:
|
05/06/2004
|
|
Title:
|
STRUCTURE AND METHOD FOR PROTECTING MEMORY CELLS FROM UV RADIATION DAMAGE AND UV RADIATION-INDUCED CHARGING DURING BACKEND PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10843289
|
Filing Dt:
|
05/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2005
| | | | |
|
Title:
|
BITLINE IMPLANT UTILIZING DUAL POLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10844116
|
Filing Dt:
|
05/12/2004
|
|
Title:
|
CASCODE AMPLIFIER CIRCUIT FOR GENERATING AND MAINTAINING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2006
|
Application #:
|
10844719
|
Filing Dt:
|
05/13/2004
|
|
Title:
|
SYSTEM AND METHOD FOR REDUCING SKEW IN COMPLEMENTARY SIGNALS THAT CAN BE USED TO SYNCHRONOUSLY CLOCK A DOUBLE DATA RATE OUTPUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
10847531
|
Filing Dt:
|
05/17/2004
|
|
Title:
|
MULTI-PORT ARBITRATION SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10847930
|
Filing Dt:
|
05/17/2004
|
|
Title:
|
METHOD OF IMPROVING LOCK ACQUISITION TIMES IN SYSTEMS WITH A NARROW FREQUENCY RANGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10848638
|
Filing Dt:
|
05/19/2004
|
|
Title:
|
SEMICONDUCTOR STRUCTURE HAVING ALIGNMENT MARKS WITH SHALLOW TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10848679
|
Filing Dt:
|
05/19/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/04/2004
| | | | |
|
Title:
|
STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
10849958
|
Filing Dt:
|
05/21/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
|
Title:
|
OPERATION MODE CONTROL CIRCUIT, MICROCOMPUTER INCLUDING THE SAME, AND CONTROL SYSTEM USING THE MICROCOMPUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2008
|
Application #:
|
10850247
|
Filing Dt:
|
05/20/2004
|
|
Title:
|
SMOOTH METAL SEMICONDUCTOR SURFACE AND METHOD FOR MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10850286
|
Filing Dt:
|
05/19/2004
|
|
Title:
|
A USB PERIPHERAL DEVICE STORING AN INDICATION OF AN OPERATING POWER MODE WHEN A HOST WENT INTO HIBERNATE AND RESTARTING AT THE POWER MODE ACCORDINGLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
10852272
|
Filing Dt:
|
05/24/2004
|
|
Title:
|
HIGH-SPEED DIFFERENTIAL LOGIC TO CMOS TRANSLATOR ARCHITECTURE WITH LOW DATA-DEPENDENT JITTER AND DUTY CYCLE DISTORTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
10852954
|
Filing Dt:
|
05/24/2004
|
|
Title:
|
COMMON MODE DETECTION AND DYNAMIC CORRECTION INPUT CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
10854781
|
Filing Dt:
|
05/27/2004
|
|
Title:
|
CHARGE/DISCHARGE CONTROL CIRCUIT AND SECONDARY BATTERY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10857039
|
Filing Dt:
|
05/28/2004
|
|
Title:
|
POWER ON RESET CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10858023
|
Filing Dt:
|
06/01/2004
|
|
Title:
|
CIRCUIT AND METHOD FOR AUTOMATICALLY SELECTING CLOCK MODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
10859369
|
Filing Dt:
|
06/01/2004
|
|
Title:
|
METHOD AND DEVICE FOR REDUCING INTERFACE AREA OF A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10860450
|
Filing Dt:
|
06/03/2004
|
|
Title:
|
METHOD OF DETERMINING VOLTAGE COMPENSATION FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
10860856
|
Filing Dt:
|
06/03/2004
|
|
Title:
|
SYSTEM FOR NOISE REDUCTION IN CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10861437
|
Filing Dt:
|
06/03/2004
|
|
Title:
|
UV-BLOCKING ETCH STOP LAYER FOR REDUCING UV-INDUCED CHARGING OF CHARGE STORAGE LAYER IN MEMORY DEVICES IN BEOL PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10861575
|
Filing Dt:
|
06/04/2004
|
|
Title:
|
METHOD AND SYSTEM FOR IMPROVING THE TOPOGRAPHY OF A MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
10861714
|
Filing Dt:
|
06/04/2004
|
|
Title:
|
BALL GRID ARRAY PACKAGE HAVING INTEGRATED ANTENNA PAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10862636
|
Filing Dt:
|
06/07/2004
|
|
Title:
|
LDC IMPLANT FOR MIRRORBIT TO IMPROVE VT ROLL-OFF AND FORM SHARPER JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
10862737
|
Filing Dt:
|
06/07/2004
|
|
Title:
|
SYNCHRONOUS MEMORY WITH A SHADOW-CYCLE COUNTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2004
|
Application #:
|
10863673
|
Filing Dt:
|
06/08/2004
|
|
Title:
|
MEMORY DEVICE AND METHODS OF USING NEGATIVE GATE STRESS TO CORRECT OVER-ERASED MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10863933
|
Filing Dt:
|
06/09/2004
|
|
Title:
|
RAMP SOURCE HOT-HOLE PROGRAMMING FOR TRAP BASED NON-VOLATILE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10864142
|
Filing Dt:
|
06/08/2004
|
|
Title:
|
MEMORY WORDLINE SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10864947
|
Filing Dt:
|
06/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
|
Title:
|
ERASE ALGORITHM FOR MULTI-LEVEL BIT FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10866510
|
Filing Dt:
|
06/11/2004
|
|
Title:
|
REGULATED, SYMMETRICAL CRYSTAL OSCILLATOR CIRCUIT AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10866985
|
Filing Dt:
|
06/15/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
A SPREAD-SPECTRUM CLOCK GENERATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10869075
|
Filing Dt:
|
06/17/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
|
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10869286
|
Filing Dt:
|
06/16/2004
|
|
Title:
|
ALIGNMENT MARKS WITH SALICIDED SPACERS BETWEEN BITLINES FOR ALIGNMENT SIGNAL IMPROVEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
10869774
|
Filing Dt:
|
06/16/2004
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH CORE AND PERIPHERY REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/2009
|
Application #:
|
10871328
|
Filing Dt:
|
06/18/2004
|
|
Title:
|
METHOD AND APPARATUS FOR SWITCHING USB DEVICES BETWEEN MULTIPLE USB HOSTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10871582
|
Filing Dt:
|
06/17/2004
|
|
Title:
|
LVDS INPUT CIRCUIT WITH EXTENDED COMMON MODE RANGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10871825
|
Filing Dt:
|
06/18/2004
|
|
Title:
|
MEMORY INTERFACE SYSTEM AND METHOD FOR REDUCING CYCLE TIME OF SEQUENTIAL READ AND WRITE ACCESSES USING SEPARATE ADDRESS AND DATA BUSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10874779
|
Filing Dt:
|
06/22/2004
|
|
Title:
|
CIRCUIT, METHOD, AND APPARATUS FOR CONTINUOUSLY VARIABLE ANALOG TO DIGITAL CONVERSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
10875561
|
Filing Dt:
|
06/23/2004
|
|
Title:
|
METHOD AND APPARATUS FOR SENSING MOVEMENT OF A HUMAN INTERFACE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
10875667
|
Filing Dt:
|
06/23/2004
|
|
Title:
|
CIRCUIT AND METHOD FOR IMPROVING FREQUENCY RANGE IN A PHASE LOCKED LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
10875888
|
Filing Dt:
|
06/24/2004
|
|
Title:
|
BUFFER CIRCUIT WITH IMPROVED DUTY CYCLE DISTORTION AND METHOD OF USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10875889
|
Filing Dt:
|
06/24/2004
|
|
Title:
|
SENSE AMPLIFIER WITH DUAL CASCODE TRANSISTORS AND IMPROVED NOISE MARGIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
10876396
|
Filing Dt:
|
06/25/2004
|
|
Title:
|
ACCOUNTING FOR THE EFFECTS OF DUMMY METAL PATTERNS IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
10876864
|
Filing Dt:
|
06/24/2004
|
|
Title:
|
AUTOMATIC BUILT-IN SELF-TEST OF LOGIC WITH SEEDING FROM ON-CHIP MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
10876944
|
Filing Dt:
|
06/25/2004
|
|
Title:
|
LOW VOLTAGE TO HIGH VOLTAGE SIGNAL LEVEL TRANSLATOR WITH IMPROVED PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
10876990
|
Filing Dt:
|
06/25/2004
|
|
Title:
|
BUILT IN SELF TEST SYSTEM AND METHOD FOR DETECTING AND CORRECTING CYCLE SLIP WITHIN A DESERIALIZER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
10877242
|
Filing Dt:
|
06/25/2004
|
|
Title:
|
METHOD OF INCREASING BATTERY LIFE IN A WIRELESS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
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Application #:
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10877291
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Filing Dt:
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06/24/2004
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Title:
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POWER MANAGEMENT BY CONSTANT AWAKE CORRELATOR
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Patent #:
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Issue Dt:
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05/08/2007
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Application #:
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10877296
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Filing Dt:
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06/24/2004
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Title:
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BINDING FOR ONE-WAY WIRELESS TRANSMISSIONS
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Patent #:
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Issue Dt:
|
08/10/2010
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Application #:
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10877313
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Filing Dt:
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06/25/2004
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Publication #:
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Pub Dt:
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12/29/2005
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Title:
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MEMORY CELL ARRAY LATCHUP PREVENTION
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Patent #:
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Issue Dt:
|
05/16/2006
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Application #:
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10877909
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Filing Dt:
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06/25/2004
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Title:
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APPARATUS AND METHOD FOR ADDRESS SELECTION
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Patent #:
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Issue Dt:
|
05/19/2009
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Application #:
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10877932
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Filing Dt:
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06/25/2004
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Title:
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CONFIGURABLE DATA PATH ARCHITECTURE AND CLOCKING SCHEME
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Patent #:
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Issue Dt:
|
06/27/2006
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Application #:
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10877981
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Filing Dt:
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06/29/2004
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Publication #:
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Pub Dt:
|
08/04/2005
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Title:
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OSCILLATION CIRCUIT AND SEMICONDUCTOR DEVICE FREE FROM THE INFLUENCE OF SOURCE VOLTAGE, TEMPERATURE AND FLUCTUATIONS IN THE INVERTER THRESHOLD VOLTAGE
|
|
|
|
|
Patent #:
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Issue Dt:
|
02/07/2006
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Application #:
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10878091
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Filing Dt:
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06/28/2004
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Publication #:
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Pub Dt:
|
11/25/2004
| | | | |
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Title:
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MEMORY DEVICE HAVING A P+ GATE AND THIN BOTTOM OXIDE AND METHOD OF ERASING SAME
|
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Patent #:
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Issue Dt:
|
09/13/2005
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Application #:
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10882538
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Filing Dt:
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06/30/2004
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Publication #:
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Pub Dt:
|
12/09/2004
| | | | |
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Title:
|
CONTROL OF MEMORY ARRAYS UTILIZING ZENER DIODE-LIKE DEVICES
|
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|
|
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Patent #:
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Issue Dt:
|
01/02/2007
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Application #:
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10883350
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Filing Dt:
|
07/01/2004
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|
Publication #:
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Pub Dt:
|
01/05/2006
| | | | |
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Title:
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SWITCHABLE MEMORY DIODE - A NEW MEMORY DEVICE
|
|
|
|
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Patent #:
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Issue Dt:
|
01/10/2006
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Application #:
|
10883924
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Filing Dt:
|
07/01/2004
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Title:
|
FLOATING GATE SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
|
07/04/2006
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Application #:
|
10885284
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Filing Dt:
|
07/06/2004
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|
Title:
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ARCHITECTURE FOR GENERATING ADAPTIVE ARBITRARY WAVEFORMS
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|
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Patent #:
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Issue Dt:
|
05/17/2005
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Application #:
|
10885944
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Filing Dt:
|
07/07/2004
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|
Title:
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CUS FORMATION BY ANODIC SULFIDE PASSIVATION OF COPPER SURFACE
|
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|
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Patent #:
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|
Issue Dt:
|
10/25/2011
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Application #:
|
10885959
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Filing Dt:
|
07/07/2004
|
|
Title:
|
SEMICONDUCTOR DEVICE BUILT ON PLASTIC SUBSTRATE
|
|
|
|
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Patent #:
|
|
Issue Dt:
|
02/15/2011
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Application #:
|
10886228
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Filing Dt:
|
07/07/2004
|
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Title:
|
IMPEDANCE MATCHING CIRCUIT
|
|
|
|
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Patent #:
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Issue Dt:
|
07/10/2007
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Application #:
|
10887585
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Filing Dt:
|
07/08/2004
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|
Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
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Title:
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BOND PAD STRUCTURE FOR COPPER METALLIZATION HAVING INCREASED RELIABILITY AND METHOD FOR FABRICATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
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Application #:
|
10887782
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Filing Dt:
|
07/09/2004
|
|
Title:
|
METHOD OF REFERENCE CELL DESIGN FOR OPTIMIZED MEMORY CIRCUIT YIELD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
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Application #:
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10888470
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Filing Dt:
|
07/09/2004
|
|
Title:
|
APPARATUS AND METHOD FOR DYNAMIC OVERCLOCKING
|
|
|
|
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Patent #:
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Issue Dt:
|
01/02/2007
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Application #:
|
10888666
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Filing Dt:
|
07/08/2004
|
|
Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
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Title:
|
METHOD AND APPARATUS FOR SCANNING A KEY OR BUTTON MATRIX
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10889245
|
Filing Dt:
|
07/12/2004
|
|
Title:
|
POWER ON RESET CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10889424
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Filing Dt:
|
07/12/2004
|
|
Title:
|
ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
10890005
|
Filing Dt:
|
07/13/2004
|
|
Title:
|
RESONATOR AND AMPLIFYING OSCILLATOR CIRCUIT HAVING A HIGH RESOLUTION SKEW-COMPENSATED FREQUENCY SYNTHESIZER INTEGRATED ON A SINGLE SUBSTRATE
|
|
|
|
|
Patent #:
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Issue Dt:
|
07/06/2010
|
Application #:
|
10891339
|
Filing Dt:
|
07/14/2004
|
|
Title:
|
FIFO MEMORY ERROR CIRCUIT AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
10896292
|
Filing Dt:
|
07/20/2004
|
|
Title:
|
APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATION REGIONS BETWEEN BIT LINES FOR INCREASED PROCESS MARGINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10896299
|
Filing Dt:
|
07/20/2004
|
|
Title:
|
METHOD FOR PROGRAMMING DUAL BIT MEMORY DEVICES TO REDUCE COMPLEMENTARY BIT DISTURBANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10896967
|
Filing Dt:
|
07/23/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
|
Title:
|
SIGNAL DETECTION APPARATUS, SIGNAL DETECTION METHOD, SIGNAL TRANSMISSION SYSTEM, AND COMPUTER READABLE PROGRAM TO EXECUTE SIGNAL TRANSMISSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2005
|
Application #:
|
10898501
|
Filing Dt:
|
07/22/2004
|
|
Title:
|
METHOD AND DEVICE TO IMPROVE USB FLASH WRITE PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
10898532
|
Filing Dt:
|
07/23/2004
|
|
Title:
|
METHOD TO PREPARE TEM SAMPLES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
10899072
|
Filing Dt:
|
07/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
SERIAL COMMUNICATION DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10899344
|
Filing Dt:
|
07/26/2004
|
|
Title:
|
THREE DIMENSIONAL POLYMER MEMORY CELL SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10899684
|
Filing Dt:
|
07/26/2004
|
|
Title:
|
METHOD FOR PULSE ERASE IN DUAL BIT MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10900832
|
Filing Dt:
|
07/28/2004
|
|
Title:
|
METHODS OF DETERMINING CHARACTERISTICS OF DOPED REGIONS ON DEVICE WAFERS, AND SYSTEM FOR ACCOMPLISHING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10909693
|
Filing Dt:
|
08/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
|
Title:
|
FLASH MEMORY UNIT AND METHOD OF PROGRAMMING A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10911630
|
Filing Dt:
|
08/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
|
Title:
|
HORIZONTAL MOS TRANSISTOR
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|
