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Patent #:
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|
Issue Dt:
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05/23/2000
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Application #:
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08939196
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Filing Dt:
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09/29/1997
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Title:
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MOS OUTPUT DRIVER, AND CIRCUIT AND METHOD OF CONTROLLING SAME
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08939838
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Filing Dt:
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09/29/1997
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Title:
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ISOLATION SCHEME BASED ON RECESSED LOCOS USING A SLOPED SI ETCH AND DRY FIELD OXIDATION
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Patent #:
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Issue Dt:
|
10/12/1999
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Application #:
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08940437
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Filing Dt:
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09/30/1997
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Title:
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SYMMETRIC LOGIC BLOCK INPUT/OUTPUT SCHEME
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Patent #:
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Issue Dt:
|
06/15/1999
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Application #:
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08940674
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Filing Dt:
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09/30/1997
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Title:
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A DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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08940682
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Filing Dt:
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09/30/1997
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Title:
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HYBRID ROUTING ARCHITECTURE FOR HIGH DENSITY COMPLEX PROGRAMMABLE LOGIC DEVICES
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Patent #:
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Issue Dt:
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12/22/1998
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Application #:
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08944904
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Filing Dt:
|
10/06/1997
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Title:
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HIGH VOLTAGE NMOS PASS GATE FOR INTEGRATED CIRCUIT WITH HIGH VOLTAGE GENERATOR AND FLASH NON-VOLATILE MEMORY DEVICE HAVING THE PASS GATE
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Patent #:
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Issue Dt:
|
03/13/2001
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Application #:
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08946030
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Filing Dt:
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10/07/1997
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Title:
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CIRCULAR PRODUCT TERM ALLOATIONS SCHEME FOR A PROGRAMMABLE DEVICE
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Patent #:
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Issue Dt:
|
03/30/1999
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Application #:
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08947123
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Filing Dt:
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10/08/1997
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Title:
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MEMORY CELL FOR STORING AT LEAST THREE LOGIC STATES
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Patent #:
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Issue Dt:
|
04/11/2000
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Application #:
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08949861
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Filing Dt:
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10/14/1997
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Title:
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VOLTAGE REFERENCE SOURCE FOR AN OVERVOLTAGE-TOLERANT BUS INTERFACE
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Patent #:
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Issue Dt:
|
06/22/1999
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Application #:
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08949863
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Filing Dt:
|
10/14/1997
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Title:
|
OVERVOLTAGE-TOLERANT INPUT OUTPUT BUFFERS HAVING A SWITCH CONFIGURED T TO ISOLATE A PUL-UP TRANSISTOR FROM A VOLTAGE SUPPLY
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08955794
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Filing Dt:
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10/22/1997
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Title:
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MEMORY CELL FABRICATION EMPLOYING AN INTERPOLY GATE DIELECTRIC ARRANGED UPON A POLISHED FLOATING GATE
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Patent #:
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Issue Dt:
|
08/01/2000
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Application #:
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08958464
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Filing Dt:
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10/27/1997
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Title:
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SYMMETRICAL NOR GATES
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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08962860
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Filing Dt:
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11/03/1997
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Title:
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STABLE ADJUSTABLE PROGRAMMING VOLTAGE SCHEME
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Patent #:
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Issue Dt:
|
10/19/1999
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Application #:
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08963843
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Filing Dt:
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11/04/1997
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Title:
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CIRCUIT AND METHOD FOR RESETTING A MICROCONTROLLER
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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08967658
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Filing Dt:
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11/10/1997
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Title:
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SKEW-REDUCTION CIRCUIT
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Patent #:
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Issue Dt:
|
10/31/2000
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Application #:
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08970107
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Filing Dt:
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11/13/1997
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Title:
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LOW TEMPERATURE METALLIZATION PROCESS
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08970448
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Filing Dt:
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11/14/1997
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Title:
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PLATE LINE SEGMENTATION IN A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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09/21/1999
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Application #:
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08970452
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Filing Dt:
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11/14/1997
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Title:
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REFERENCE CELL FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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03/09/1999
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Application #:
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08970453
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Filing Dt:
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11/14/1997
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Title:
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SENSING METHODOLOGY FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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04/06/1999
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Application #:
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08970454
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Filing Dt:
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11/14/1997
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Title:
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COLUMN DECODER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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08970518
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Filing Dt:
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11/14/1997
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Title:
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REFERENCE CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
|
10/19/1999
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Application #:
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08970519
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Filing Dt:
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11/14/1997
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Title:
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SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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08970520
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Filing Dt:
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11/14/1997
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Title:
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MEMORY CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
|
11/02/1999
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Application #:
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08970522
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Filing Dt:
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11/14/1997
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Title:
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PLATE LINE DRIVER CIRCUIT FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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08971627
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Filing Dt:
|
11/17/1997
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Title:
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DYNAMIC PULL-UP SUPPRESSOR FOR COLUMN REDUNDANCY WRITE SCHEMES WITH REDUNDANT DATA LINES
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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08974736
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Filing Dt:
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11/19/1997
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Title:
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UNIVERSAL SERIAL BUS TO PARALLEL BUS SIGNAL CONVERTER AND METHOD OF CONVERSION
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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08974971
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Filing Dt:
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11/20/1997
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Title:
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NON-VOLATILE MEMORY SYSTEM HAVING A PROGRAMMABLY SELECTABLE BOOT CODE SECTION SIZE
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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08978107
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Filing Dt:
|
11/25/1997
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Title:
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METHOD OF FABRICATING A HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
|
02/15/2000
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Application #:
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08978398
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Filing Dt:
|
11/25/1997
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Title:
|
METHOD OF FABRICATING AN OXYNITRIDE-CAPPED HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY.
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Patent #:
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Issue Dt:
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01/25/2000
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Application #:
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08982186
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Filing Dt:
|
12/17/1997
|
Title:
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METHOD FOR FORMING A LOW BARRIER HEIGHT OXIDE LAYER ON A SILICON SUBSTRATE
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Patent #:
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Issue Dt:
|
05/09/2000
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Application #:
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08982730
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Filing Dt:
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12/02/1997
|
Title:
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METHOD AND APPARATUS FOR GENERATING TEST PATTERN FOR SECQUENCE DETECTION
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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08985890
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Filing Dt:
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12/05/1997
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Title:
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PARALLEL TEST FOR ASYNCHRONOUS MEMORY
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Patent #:
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Issue Dt:
|
11/09/1999
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Application #:
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08986160
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Filing Dt:
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12/05/1997
|
Title:
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SIDEWALL SPACER FOR PROTECTING TUNNEL OXIDE DURING ISOLATION TRENCH FORMATION IN SELF-ALIGNED FLASH MEMORY CORE
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Patent #:
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Issue Dt:
|
11/02/1999
|
Application #:
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08986371
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Filing Dt:
|
12/08/1997
|
Title:
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METHOD OF REDUCING IMPURITY CONTAMINATION IN SEMICONDUCTOR PROCESS CHAMBERS
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Patent #:
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Issue Dt:
|
04/25/2000
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Application #:
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08986440
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Filing Dt:
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12/08/1997
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Title:
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CURRENTSENSING AMPLIFIER WITH FEEDBACK
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Patent #:
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Issue Dt:
|
12/14/1999
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Application #:
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08986860
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Filing Dt:
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12/08/1997
|
Title:
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METHOD OF ELIMINATING POLY STRINGER IN A MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/04/2000
|
Application #:
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08986951
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Filing Dt:
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12/08/1997
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Title:
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ELIMINATION OF POLY STRINGERS WITH STRAIGHT POLY PROFILE
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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08986953
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Filing Dt:
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12/08/1997
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Title:
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REDUCTION OF ONO FENCE DURING SELF-ALIGNED ETCH TO ELIMINATE POLY STRINGERS
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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08988942
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Filing Dt:
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12/11/1997
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Title:
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APPARATUS AND METHOD FOR CORRECTING DATA IN A NON- VOLATILE RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
|
12/28/1999
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Application #:
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08989517
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Filing Dt:
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12/12/1997
|
Title:
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A CHARGING AND DISCHARGING DEVICE FOR AN ELECTRONIC APPARATUS, AND AN ELECTRONIC APPARATUS INCLUDING THE SAME, UTILIZING A CHARGING DEVICE PROVIDING A CONSTANT CHARGING CURRENT
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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08989707
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Filing Dt:
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12/12/1997
|
Title:
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LOW POWER BUFFER CIRCUIT AND METHOD FOR GENERATING A COMMON-MODE OUTPUT ABSENT PROCESS-INDUCED MISMATCH ERROR
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Patent #:
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Issue Dt:
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12/14/1999
|
Application #:
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08989820
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Filing Dt:
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12/12/1997
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Title:
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SEMICONDUCTOR ISOLATION PROCESS TO MINIMIZE WEAK OXIDE PROBLEMS
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Patent #:
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Issue Dt:
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08/17/1999
|
Application #:
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08990126
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Filing Dt:
|
12/12/1997
|
Title:
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COMBINATIONAL LOGIC FEEDBACK CIRCUIT TO ENSURE CORRECT POWER-ON-RESET OF A FOUR-BIT SYNCHRONOUS SHIFT REGISTER
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Patent #:
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Issue Dt:
|
11/30/1999
|
Application #:
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08991052
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Filing Dt:
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12/16/1997
|
Title:
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SEMICONDUCTOR DEVICE WITH MULTIPLE CONTACT SIZES
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Patent #:
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Issue Dt:
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10/05/1999
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Application #:
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08991231
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Filing Dt:
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12/16/1997
|
Title:
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WRITE ENABLING CIRCUITRY FOR A SEMICONDUCT0R MEMORY
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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08991232
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Filing Dt:
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12/16/1997
|
Title:
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MICROCONTROLLER WITH PROGRAMMABLE LOGIC ON A SINGLE CHIP
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Patent #:
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Issue Dt:
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06/06/2000
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Application #:
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08991299
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Filing Dt:
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12/16/1997
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Title:
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INTERLEVEL DIELECTRIC THICKNESS MONITOR FOR COMPLEX SEMICONDUCTOR CHIPS
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Patent #:
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Issue Dt:
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01/12/1999
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Application #:
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08991466
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Filing Dt:
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12/16/1997
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Title:
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PROGRAMMING OF MEMORY CELLS USING CONNECTED FLOATING GATE ANALOG REFERENCE CELL
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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08991687
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Filing Dt:
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12/16/1997
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Title:
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NON-SELF-ALIGNED SIDE CHANNEL IMPLANTS FOR FLASH MEMORY CELLS
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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08991845
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Filing Dt:
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12/16/1997
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Title:
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APPARATUS AND METHOD FOR SHORTING RESTRANSMIT RECOVERY TIMES UTILIZING CACHE MEMORY IN HIGH SPEED FIFO
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Patent #:
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Issue Dt:
|
05/25/1999
|
Application #:
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08992077
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Filing Dt:
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12/17/1997
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Title:
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METHOD TO IMPROVE TESTING SPEED OF MEMORY
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Patent #:
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Issue Dt:
|
12/21/1999
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Application #:
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08992199
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Filing Dt:
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12/17/1997
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Title:
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CIRCUIT AND METHOD FOR INSTRUCTION CONTROLLABLE SLEW RATE OF BIT LINE DRIVER
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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08992536
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Filing Dt:
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12/17/1997
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Title:
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METHOD FOR FULLY PLANARIZED CONDUCTIVE LINE FOR A STACK GATE
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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08992616
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Filing Dt:
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12/17/1997
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Title:
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METHOD AND SYSTEM FOR PROVIDING LOCALIZED GATE EDGE ROUNDING WITH MINIMAL ENCROACHMENT AND GATE EDGE LIFTING
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Patent #:
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Issue Dt:
|
08/15/2000
|
Application #:
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08992618
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Filing Dt:
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12/17/1997
|
Title:
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METHOD AND SYSTEM FOR PROVIDING A DRAIN SIDE POCKET IMPLANT
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Patent #:
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Issue Dt:
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09/07/1999
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Application #:
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08992622
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Filing Dt:
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12/17/1997
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Title:
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METHOD AND SYSTEM FOR SELECTED SOURCE DURING READ AND PROGRAMMING OF FLASH MEMORY
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08992950
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Filing Dt:
|
12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR FORMING A FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
10/26/1999
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Application #:
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08992951
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Filing Dt:
|
12/18/1997
|
Title:
|
METHODS AND ARRANGEMENTS FOR FORMING A TAPERED FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
07/10/2001
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Application #:
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08992960
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Filing Dt:
|
12/18/1997
|
Title:
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METHODS AND ARRANGEMENTS FOR IMPROVED FORMATION OF CONTROL AND FLOATING GATES IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
09/26/2000
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Application #:
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08992961
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Filing Dt:
|
12/18/1997
|
Title:
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NON-VOLATILE TRENCH SEMICONDUCTOR DEVICE HAVING A SHALLOW DRAIN REGION
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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08993036
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Filing Dt:
|
12/18/1997
|
Title:
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METHOD AND APPARATUS FOR OBTAINING TWO-OR THREE-DEMENSIONAL INFORMATION FROM SCANNING ELECTRON MICROSCOPY
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Patent #:
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Issue Dt:
|
02/06/2001
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Application #:
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08993062
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Filing Dt:
|
12/18/1997
|
Title:
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DEVICE INITIALIZING SYSTEM WITH PROGRAMMABLE ARRAY LOGIC CONFIGURED TO CAUSE NON-VOLATILE MEMORY TO OUTPUT ADDRESS AND DATA INFORMATION TO THE DEVICE IN A PRESCRIBED SEQUENCE
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Patent #:
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Issue Dt:
|
05/08/2001
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Application #:
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08993149
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Filing Dt:
|
12/18/1997
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Title:
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METHODOLOGY FOR ACHIEVING DUAL FIELD OXIDE THICKNESSES
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08993343
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Filing Dt:
|
12/18/1997
|
Title:
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MANUFACTURING PROCESS TO ELIMINATE POLYSTRINGERS IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
|
08/28/2001
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Application #:
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08993344
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Filing Dt:
|
12/18/1997
|
Title:
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MANUFACTURING PROCESS TO ELIMINATE ONO FENCE MATERIAL IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
|
12/23/2003
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Application #:
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08993368
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Filing Dt:
|
12/18/1997
|
Title:
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NOVEL NAND TYPE CORE CELL STRUCTURE FOR A HIGH DENSITY FLASH MEMORY DEVICE HAVING A UNIQUE SELECT GATE TRANSISTOR CONFIGURATION
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Patent #:
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Issue Dt:
|
05/16/2000
|
Application #:
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08993409
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Filing Dt:
|
12/18/1997
|
Title:
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METHODS FOR FORMING A CONTROL GATE APPARATUS IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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08993443
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Filing Dt:
|
12/18/1997
|
Title:
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NITROGEN ION IMPLANTED AMORPHOUS SILICON TO PRODUCE OXIDATION RESISTANT AND FINER GRAIN POLYSILICON BASED FLOATING GATES
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Patent #:
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Issue Dt:
|
10/31/2000
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Application #:
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08993444
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Filing Dt:
|
12/18/1997
|
Title:
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IN SITU P DOPED AMORPHOUS SILICON BY NH3 TO FORM OXIDATION RESISTANT AND FINER GRAIN FLOATING GATES.
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Patent #:
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Issue Dt:
|
08/17/1999
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Application #:
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08993599
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Filing Dt:
|
12/18/1997
|
Title:
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METHOD AND SYSTEM FOR SOURCE ONLY REOXIDATION AFTER JUNCTION IMPLANT FOR FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
|
02/15/2000
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Application #:
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08993600
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Filing Dt:
|
12/18/1997
|
Title:
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METHOD AND SYSTEM FOR USING A SPACER TO OFFSET IMPLANT DAMAGE AND REDUCE LATERAL DIFFUSION IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
|
12/21/1999
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Application #:
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08993634
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Filing Dt:
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12/18/1997
|
Title:
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SPLIT VOLTAGE FOR NAND FLASH
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Patent #:
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Issue Dt:
|
06/27/2000
|
Application #:
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08993716
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Filing Dt:
|
12/18/1997
|
Title:
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METHODOLOGY FOR ACHIEVING DUAL GATE OXIDE THICKNESSES
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|
Patent #:
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01/18/2000
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08993787
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12/19/1997
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Title:
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12/14/1999
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08993890
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12/18/1997
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Title:
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NON- VOLATILE TRENCH SEMICONDUCTOR DEVICE
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12/11/2001
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08994140
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12/19/1997
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Title:
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METHOD FOR LATERALLY PEAKED SOURCE DOPING PROFILES FOR BETTER ERASE CONTROL IN FLASH MEMORY DEVICES
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02/08/2000
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08995381
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12/22/1997
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STAGGERED BITLINE PRECHARGE SCHEME
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09/26/2000
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08995494
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12/22/1997
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CURRENT SENSING GATED CURRENT SOURCE FOR DELAY REDUCTION IN A UNIVERSAL SERIAL BUS (USB) LOW SPEED OUTPUT DRIVER
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11/14/2000
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12/24/1997
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OPTIMIZED PROGRAMMING/ERASE PARAMETERS FOR PROGRAMMABLE DEVICES
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09/28/1999
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12/29/1997
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12/26/2000
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12/30/1997
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10/26/1999
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01/05/1998
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05/22/2001
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01/13/1998
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02/13/2001
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01/14/1998
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06/14/2005
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01/14/1998
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04/06/1999
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01/15/1998
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12/10/2002
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01/16/1998
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12/14/1999
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01/16/1998
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02/29/2000
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01/27/1998
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06/22/1999
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01/30/1998
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01/04/2000
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02/02/1998
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10/05/1999
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02/05/1998
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07/17/2001
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02/10/1998
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08/21/2001
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02/10/1998
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06/27/2000
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02/10/1998
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05/30/2000
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02/11/1998
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NON-VOLATILE MEMORY CELL HAVING A HIGH COUPLING RATIO
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03/30/1999
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02/13/1998
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10/24/2000
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02/13/1998
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07/13/1999
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02/19/1998
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08/08/2000
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02/27/1998
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MULTIPLE CHIP HYBRID PACKAGE USING BUMP TECHNOLOGY
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