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Reel/Frame:035390/0388   Pages: 247
Recorded: 04/03/2015
Attorney Dkt #:040981-0072
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 5804
Page 14 of 59
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
1
Patent #:
Issue Dt:
08/21/2001
Application #:
09464225
Filing Dt:
12/15/1999
Title:
CORROSION SENSITIVITY STRUCTURES FOR VIAS AND CONTACT HOLES IN INTEGRATED CIRCUITS
2
Patent #:
Issue Dt:
07/06/2004
Application #:
09464297
Filing Dt:
12/15/1999
Title:
PROCESS FOR ETCHING A CONTROLLABLE THICKNESS OF OXIDE ON AN INTEGRATED CIRCUIT STRUCTURE ON A SEMICONDUCTOR SUBSTRATE USING NITROGEN PLASMA AND PLASMA AND AN RF BIAS APPLIED TO THE SUBSTRATE
3
Patent #:
Issue Dt:
07/01/2003
Application #:
09464623
Filing Dt:
12/16/1999
Title:
PROGRAMMABLE ASIC
4
Patent #:
Issue Dt:
08/13/2002
Application #:
09464741
Filing Dt:
12/16/1999
Title:
METHOD FOR PROGRAMMING AN FPGA AND IMPLEMENTING AN FPGA INTERCONNECT USING CLOCK CONTROLS
5
Patent #:
Issue Dt:
11/08/2005
Application #:
09465131
Filing Dt:
12/16/1999
Title:
METHOD AND APPARATUS FOR THERMAL PROFILING OF FLIP-CHIP PACKAGES
6
Patent #:
Issue Dt:
05/28/2002
Application #:
09465132
Filing Dt:
12/16/1999
Title:
METHOD AND APPARATUS FOR CLEANING AND REMOVING FLUX FROM AN ELECTRONIC COMPONENT PACKAGE
7
Patent #:
Issue Dt:
11/20/2001
Application #:
09465425
Filing Dt:
12/20/1999
Title:
METHOD AND STRUCTURE FOR REDUCING THE INCIDENCE OF VOIDING IN AN UNDERFILL LAYER OF AN ELECTRONIC COMPONENT PACKAGE
8
Patent #:
Issue Dt:
04/09/2002
Application #:
09465618
Filing Dt:
12/17/1999
Title:
PATCHING DEGRADED VIDEO DATA
9
Patent #:
Issue Dt:
01/07/2003
Application #:
09466389
Filing Dt:
12/17/1999
Title:
MULTI-CONDITION BISR TEST MODE FOR MEMORIES WITH REDUNDANCY
10
Patent #:
Issue Dt:
10/09/2001
Application #:
09466519
Filing Dt:
12/17/1999
Title:
FAST COMPARATOR SUITABLE FOR BIST AND BISR APPLICATIONS
11
Patent #:
Issue Dt:
05/01/2001
Application #:
09467081
Filing Dt:
12/10/1999
Title:
PLASTIC BALL GRID ARRAY PACKAGE WITH STRIP LINE CONFIGURATION
12
Patent #:
Issue Dt:
10/09/2001
Application #:
09467193
Filing Dt:
12/20/1999
Title:
HOST REGISTER INTERFACE TESTING ON BIT STREAM BASED SYSTEMS
13
Patent #:
Issue Dt:
05/08/2001
Application #:
09467340
Filing Dt:
12/20/1999
Title:
NON-LINEAR CIRCUIT ELEMENTS ON INTEGRATED CIRCUITS
14
Patent #:
Issue Dt:
12/30/2003
Application #:
09467461
Filing Dt:
12/20/1999
Title:
METHODOLOGY FOR PROVIDING PERSISTENT TARGET IDENTIFICATION IN A FIBRE CHANNEL ENVIRONMENT
15
Patent #:
Issue Dt:
04/23/2002
Application #:
09467622
Filing Dt:
12/20/1999
Title:
METHOD AND APPARATUS FOR DETECTING PRESENCE OF RESIDUAL POLISHING SLURRY SUBSEQUENT TO POLISHING OF A SEMICONDUCTOR WAFER
16
Patent #:
Issue Dt:
07/24/2001
Application #:
09468711
Filing Dt:
12/21/1999
Title:
NON-UNIFORM DELAY STAGES TO INCREASE THE OPERATING FREQUENCY RANGE OF DELAY LINES
17
Patent #:
Issue Dt:
03/01/2005
Application #:
09468746
Filing Dt:
12/21/1999
Title:
RECEIVE DESERIALIZER CIRCUIT FOR FRAMING PARALLEL DATA
18
Patent #:
Issue Dt:
01/29/2002
Application #:
09469579
Filing Dt:
12/22/1999
Title:
METHOD OF FABRICATING AN INDIUM FIELD IMPLANT FOR PUNCHTHROUGH PROTECTION IN SEMICONDUCTOR DEVICES
19
Patent #:
Issue Dt:
09/11/2001
Application #:
09469730
Filing Dt:
12/21/1999
Title:
RECEIVE DESERIALIZER FOR REGENERATING PARALLEL DATA SERIALLY TRANSMITTED OVER MULTIPLE CHANNELS
20
Patent #:
Issue Dt:
09/23/2003
Application #:
09470004
Filing Dt:
12/22/1999
Title:
SYNCHRONIZATION OF SUPER FRAMES IN AN INTEGRATED SERVICES DIGITAL BROADCASTING FOR SATELLITIES ISDB-S SYSTEM
21
Patent #:
Issue Dt:
09/23/2003
Application #:
09470362
Filing Dt:
12/22/1999
Title:
CYCLE MODELING IN CYCLE ACCURATE SOFTWARE SIMULATORS OF HARDWARE MODULES FOR SOFTWARE/SOFTWARE CROSS-SIMULATION AND HARDWARE/SOFTWARE CO-SIMULATION
22
Patent #:
Issue Dt:
07/22/2003
Application #:
09471642
Filing Dt:
12/23/1999
Title:
DUAL-PORT SCSI SUB-SYSTEM WITH FAIL-OVER CAPABILITIES
23
Patent #:
Issue Dt:
08/14/2001
Application #:
09471842
Filing Dt:
12/23/1999
Title:
METHOD AND APPARATUS FOR MAINTAINING TEST DATA DURING FABRICATION OF A SEMICONDUCTOR WAFER
24
Patent #:
Issue Dt:
07/01/2003
Application #:
09472670
Filing Dt:
12/27/1999
Title:
FADING OF MAIN VIDEO SIGNAL WITHOUT AFFECTING DISPLAY OF SUPERIMPOSED VIDEO SIGNAL
25
Patent #:
Issue Dt:
06/24/2003
Application #:
09473777
Filing Dt:
12/29/1999
Title:
POWER CONTROL DURING INTER-GENERATION SOFT HANDOFFS
26
Patent #:
Issue Dt:
11/27/2001
Application #:
09474666
Filing Dt:
12/29/1999
Title:
DUAL NITROGEN IMPLANTATION TECHNIQUES FOR OXYNITRIDE FORMATION IN SEMICONDUCTOR DEVICES
27
Patent #:
Issue Dt:
08/03/2004
Application #:
09476395
Filing Dt:
12/30/1999
Title:
METHOD AND FORMAT FOR READING AND WRITING IN A MULTILEVEL OPTICAL DATA SYSTEM
28
Patent #:
Issue Dt:
12/17/2002
Application #:
09477170
Filing Dt:
01/04/2000
Title:
LOCAL INTERCONNECTION PROCESS FOR PREVENTING DOPANT CROSS DIFFUSION IN SHARED GATE ELECTRODES
29
Patent #:
Issue Dt:
03/30/2004
Application #:
09477317
Filing Dt:
01/04/2000
Title:
INTEGRATED SERVICES DIGITAL BROADCASTING DEINTERLEAVER ARCHITECTURE
30
Patent #:
Issue Dt:
04/27/2004
Application #:
09477658
Filing Dt:
01/05/2000
Title:
LOWER-JITTER PHASE-LOCKED LOOP
31
Patent #:
Issue Dt:
01/28/2003
Application #:
09477692
Filing Dt:
01/06/2000
Title:
SYSTEM FOR MODELIING A PROCESSOR -ENCODER INTERFACE BY COUNTING NUMBER OF FAST CLOCK CYCLES OCCURING IN ONE SLOWER CLOCK CYCLE AND TRIGGERING A DOMAIN MODULE IF FAST CLOCK REACHES THE CORRESPONDING NUMBER OF CYCLES
32
Patent #:
Issue Dt:
02/12/2002
Application #:
09478164
Filing Dt:
01/05/2000
Title:
SUBSTRATE POSITION LOCATION SYSTEM LSI LOGIC CORPORATION
33
Patent #:
Issue Dt:
08/06/2002
Application #:
09478972
Filing Dt:
01/06/2000
Title:
INTERPOSER TAPE FOR SEMICONDUCTOR PACKAGE
34
Patent #:
Issue Dt:
05/25/2004
Application #:
09480220
Filing Dt:
01/10/2000
Title:
HYBRID STATE MACHINE FOR FRAME SYNCHRONIZATION
35
Patent #:
Issue Dt:
07/03/2001
Application #:
09481891
Filing Dt:
01/12/2000
Title:
BUILT-IN SELF-TEST UNIT HAVING A RECONFIGURABLE DATA RETENTION TEST
36
Patent #:
Issue Dt:
06/11/2002
Application #:
09482291
Filing Dt:
01/13/2000
Title:
CURRENT-MODE PEAK DETECTOR
37
Patent #:
Issue Dt:
08/24/2004
Application #:
09484630
Filing Dt:
01/18/2000
Title:
METHOD AND APPARATUS FOR ESTIMATING THE LENGTH OF A TRANSMISSION LINE
38
Patent #:
Issue Dt:
09/10/2002
Application #:
09487984
Filing Dt:
01/20/2000
Title:
MULTIPLE METAL ETCHANT SYSTEM FOR INTEGRATED CIRCUITS
39
Patent #:
Issue Dt:
08/28/2001
Application #:
09488438
Filing Dt:
01/20/2000
Title:
Loose die fixture
40
Patent #:
Issue Dt:
09/24/2002
Application #:
09492881
Filing Dt:
01/26/2000
Title:
I/O DEVICE LAYOUT DURING INTEGRATED CIRCUIT DESIGN
41
Patent #:
Issue Dt:
09/03/2002
Application #:
09493467
Filing Dt:
01/28/2000
Title:
SPARE CELLS PLACEMENT METHODOLOGY
42
Patent #:
Issue Dt:
06/04/2002
Application #:
09494070
Filing Dt:
01/28/2000
Title:
HEAT DISSIPATING APPARATUS AND METHOD FOR ELECTRONIC COMPONENTS
43
Patent #:
Issue Dt:
04/24/2001
Application #:
09494477
Filing Dt:
01/31/2000
Title:
Bus bridge architecture for a data processing system capable of sharing processing load among a plurality of device
44
Patent #:
Issue Dt:
07/23/2002
Application #:
09494605
Filing Dt:
01/31/2000
Title:
SYSTEMATIC SKEW REDUCTION THROUGH BUFFER RESIZING
45
Patent #:
Issue Dt:
02/27/2001
Application #:
09495512
Filing Dt:
02/01/2000
Title:
INTEGRATED CIRCUIT HAVING LOW VOLTAGE AND HIGH VOLTAGE DEVICES ON A COMMON SEMICONDUCTOR SUBSTRATE
46
Patent #:
Issue Dt:
02/25/2003
Application #:
09496031
Filing Dt:
02/02/2000
Title:
RAID LUN CREATION USING PROPORTIONAL DISK MAPPING
47
Patent #:
Issue Dt:
08/19/2003
Application #:
09496387
Filing Dt:
02/02/2000
Title:
GENERATING A MULTILEVEL CALIBRATION SEQUENCE FOR PRECOMPENSATION
48
Patent #:
Issue Dt:
08/05/2003
Application #:
09496897
Filing Dt:
02/02/2000
Title:
DC CONTROL OF A MULTILEVEL SIGNAL
49
Patent #:
Issue Dt:
09/06/2005
Application #:
09496898
Filing Dt:
02/02/2000
Title:
WRITE COMPENSATION FOR A MULTI-LEVEL DATA STORAGE SYSTEM
50
Patent #:
Issue Dt:
01/07/2003
Application #:
09496971
Filing Dt:
02/02/2000
Title:
INTERCONNECT-EMBEDDED METAL-INSULATOR-METAL CAPACITOR
51
Patent #:
Issue Dt:
01/07/2003
Application #:
09497521
Filing Dt:
02/04/2000
Title:
PERIPHERAL PARTITIONING AND TREE DECOMPOSITION FOR PARTIAL SCAN
52
Patent #:
Issue Dt:
06/05/2001
Application #:
09497652
Filing Dt:
02/03/2000
Title:
Current stacked bandgap reference voltage source
53
Patent #:
Issue Dt:
01/09/2001
Application #:
09498492
Filing Dt:
02/03/2000
Title:
Circuit and method for accurately mirroring currents in application specific integrated circuits
54
Patent #:
Issue Dt:
01/01/2002
Application #:
09499801
Filing Dt:
02/08/2000
Title:
Interposer for semiconductor package assembly
55
Patent #:
Issue Dt:
10/14/2003
Application #:
09501807
Filing Dt:
02/10/2000
Title:
DECODING CIRCUIT FOR MEMORIES WITH REDUNDANCY
56
Patent #:
Issue Dt:
04/24/2001
Application #:
09503691
Filing Dt:
02/14/2000
Title:
Advanced modular cell placement system with overlap remover with minimal noise
57
Patent #:
Issue Dt:
07/23/2002
Application #:
09507042
Filing Dt:
02/18/2000
Title:
SHALLOW TRENCH ISOLATION CHEMICAL-MECHANICAL POLISHING PROCESS
58
Patent #:
Issue Dt:
01/20/2004
Application #:
09510009
Filing Dt:
02/22/2000
Title:
PARALLEL TESTING OF A MULTIPORT MEMORY
59
Patent #:
Issue Dt:
10/16/2001
Application #:
09513018
Filing Dt:
02/25/2000
Title:
Comparator metastability performance from an enhanced comparator detection circuit
60
Patent #:
Issue Dt:
11/19/2002
Application #:
09515250
Filing Dt:
02/29/2000
Title:
4K DERATING SCHEME FOR PROPAGATION DELAY AND SERUP/HOLD TIME COMPUTATION
61
Patent #:
Issue Dt:
11/16/2004
Application #:
09515376
Filing Dt:
02/29/2000
Title:
4 POINT DERATING SCHEMEM FOR PROPAGATION DELAY AND SETUP/HOLD TIME COMPUTATION
62
Patent #:
Issue Dt:
11/12/2002
Application #:
09517150
Filing Dt:
03/02/2000
Title:
CAPACITOR HAVING A TANTALUM LOWER ELECTRODE AND METHOD OF FORMING THE SAME
63
Patent #:
Issue Dt:
08/12/2003
Application #:
09517398
Filing Dt:
03/02/2000
Title:
MODIFIED FIRST-ORDER DIGITAL PLL WITH FREQUENCY LOCKING CAPABILITY
64
Patent #:
Issue Dt:
09/30/2003
Application #:
09517817
Filing Dt:
03/02/2000
Title:
FIBRE CHANNEL SERVICE PARAMETER CACHE
65
Patent #:
Issue Dt:
09/05/2006
Application #:
09517884
Filing Dt:
03/03/2000
Title:
IEEE 1394 LINK LAYER CHIP WITH "5C" AUTHENTICATION AND KEY EXCHANGE ACCELERATOR
66
Patent #:
Issue Dt:
07/02/2002
Application #:
09521312
Filing Dt:
03/09/2000
Title:
PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NITRIDATION OF UPPER SURFACE OF GATE OXIDE TO FORM BARRIER OF NITROGEN ATOMS IN UPPER SURFACE REGION OF GATE OXIDE, AND RESULTING PRODUCT
67
Patent #:
Issue Dt:
03/19/2002
Application #:
09521811
Filing Dt:
03/09/2000
Title:
Integrated circuit clock distribution system
68
Patent #:
Issue Dt:
04/08/2003
Application #:
09523224
Filing Dt:
03/10/2000
Title:
INTEGRATED CIRCUIT HAVING ON-CHIP CAPACITORS FOR SUPPLYING POWER TO PORTIONS OF THE CIRCUIT REQUIRING HIGH-TRANSIENT PEAK POWER
69
Patent #:
Issue Dt:
02/25/2003
Application #:
09523489
Filing Dt:
03/10/2000
Title:
SECAM VIDEO STANDARD CHROMA MODULATION CIRCUIT
70
Patent #:
Issue Dt:
10/23/2001
Application #:
09523505
Filing Dt:
03/10/2000
Title:
Slim rate/propagation delay selection circuit
71
Patent #:
Issue Dt:
05/15/2001
Application #:
09524734
Filing Dt:
03/14/2000
Title:
Multi-port semiconductor memory and compiler having capacitance compensation
72
Patent #:
Issue Dt:
07/16/2002
Application #:
09524831
Filing Dt:
03/14/2000
Title:
HYSTERESIS IN AN OVERSAMPLED DATA CONVETER
73
Patent #:
Issue Dt:
08/27/2002
Application #:
09525489
Filing Dt:
03/15/2000
Title:
ENCAPSULATED-METAL VERTICAL-INTERDIGITATED CAPACITOR AND DAMASCENE METHOD OF MANUFACTURING SAME
74
Patent #:
Issue Dt:
08/14/2001
Application #:
09525995
Filing Dt:
03/15/2000
Title:
Circuit and method for control of amplifier operating angle
75
Patent #:
Issue Dt:
09/16/2003
Application #:
09532148
Filing Dt:
03/21/2000
Title:
DATA TRANSMISSION BUFFER HAVING FRAME COUNTER FEEDBACK FOR RE-TRANSMITTING ABORTED DATA FRAMES
76
Patent #:
Issue Dt:
07/10/2001
Application #:
09534652
Filing Dt:
03/24/2000
Title:
Endpoint detection method and apparatus which utilize an endpoint polishing layer of catalyst material
77
Patent #:
Issue Dt:
07/02/2002
Application #:
09534907
Filing Dt:
03/23/2000
Title:
SELF-ALIGNED FUSE STRUCTURE AND METHOD WITH DUAL-THICKNESS DIELECTRIC
78
Patent #:
Issue Dt:
11/06/2001
Application #:
09536527
Filing Dt:
03/28/2000
Title:
Passive sample and hold in an active switched capacitor circuit
79
Patent #:
Issue Dt:
06/03/2003
Application #:
09540197
Filing Dt:
03/31/2000
Title:
USE OF A SCAN CHAIN FOR CONFIGURATION OF BIST UNIT OPERATION
80
Patent #:
Issue Dt:
01/30/2001
Application #:
09542078
Filing Dt:
04/03/2000
Title:
Self-timing circuit for semiconductor memory devices
81
Patent #:
Issue Dt:
02/12/2002
Application #:
09543412
Filing Dt:
04/05/2000
Title:
Process for treating damaged surfaces of low k carbon doped silicon oxide dielectric material after plasma etching and plasma cleaning steps
82
Patent #:
Issue Dt:
10/07/2003
Application #:
09543647
Filing Dt:
04/05/2000
Title:
SERVER FOR OPERATION WITH A LOW-COST MULTIMEDIA
83
Patent #:
Issue Dt:
07/01/2003
Application #:
09546786
Filing Dt:
04/11/2000
Title:
PCI BUS SYSTEM TESTING AND VERICATION APPARATUS AND METHOD
84
Patent #:
Issue Dt:
07/17/2001
Application #:
09548498
Filing Dt:
04/13/2000
Title:
Phase-locked loop with built-in self-test of phase margin and loop gain
85
Patent #:
Issue Dt:
10/21/2003
Application #:
09548507
Filing Dt:
04/13/2000
Title:
A SYSTEM FOR MEASURING PHASE ERROR BETWEEN TWO CLOCKS BY USING A PLURALITY OF PHASE LATCHES WITH DIFFERENT RESPECTIVE PHASE DELAYS
86
Patent #:
Issue Dt:
10/28/2003
Application #:
09549621
Filing Dt:
04/14/2000
Title:
BUILT-IN SELF-REPAIR OF SEMICONDUCTOR MEMORY WITH REDUNDANT ROW TESTING USING BACKGROUND PATTERN
87
Patent #:
Issue Dt:
12/11/2001
Application #:
09550679
Filing Dt:
04/17/2000
Title:
Power-on reset cell
88
Patent #:
Issue Dt:
11/25/2003
Application #:
09550764
Filing Dt:
04/17/2000
Title:
AUTOMATED SYSTEM FOR INSERTING AND READING OF PROBE POINTS IN SILICON EMBEDDED TESTBENCHES
89
Patent #:
Issue Dt:
01/01/2002
Application #:
09552266
Filing Dt:
04/19/2000
Title:
Compensation capacitance for minimizing bit line coupling in multiport memory
90
Patent #:
Issue Dt:
07/06/2010
Application #:
09553140
Filing Dt:
04/20/2000
Title:
DETERMINATION OF FILM THICKNESS DURING CHEMICAL MECHANICAL POLISHING
91
Patent #:
Issue Dt:
04/15/2003
Application #:
09557946
Filing Dt:
04/24/2000
Title:
METHOD AND APPARATUS FOR ENHANCING IMAGE CONTRAST USING INTENSITY FILTRATION
92
Patent #:
Issue Dt:
06/24/2003
Application #:
09559193
Filing Dt:
04/27/2000
Title:
ARBITRATION CIRCUIT WITH PLURAL ARBITRATION PROCESSORS USING MEMORY BANK HISTORY
93
Patent #:
Issue Dt:
10/29/2002
Application #:
09564062
Filing Dt:
05/03/2000
Title:
WIRE ROUTING TO CONTROL SKEW
94
Patent #:
Issue Dt:
11/04/2003
Application #:
09567203
Filing Dt:
05/08/2000
Title:
PAD CELL CIRCUIT-INTEGRATED, DIFFERENTIAL-SIGNAL EQUALIZATION RECEIVER FOR INTEGRATED CIRCUIT AND METHOD OF BOOSTING AND EQUALIZING HIGH FREQUENCY DIFFERENTIAL SIGNALS
95
Patent #:
Issue Dt:
05/04/2004
Application #:
09568049
Filing Dt:
05/10/2000
Title:
PERIPHERAL PARTITIONING AND TREE DECOMPOSITION FOR PARTIAL SCAN
96
Patent #:
Issue Dt:
05/04/2004
Application #:
09568739
Filing Dt:
05/11/2000
Title:
REDUCING POWER CONSUMPTION AND SIMULTANEOUS SWITCHING IN A BUS INTERFACE
97
Patent #:
Issue Dt:
06/28/2005
Application #:
09568996
Filing Dt:
05/11/2000
Title:
DISK ARRAY STORAGE SUBSYSTEM WITH PARITY ASSIST CIRCUIT THAT USES SCATTER-GATHER LIST
98
Patent #:
Issue Dt:
11/23/2004
Application #:
09569194
Filing Dt:
05/11/2000
Title:
SHARED RESOURCE MANAGER FOR MULTIPROCESSOR COMPUTER SYSTEM
99
Patent #:
Issue Dt:
07/08/2003
Application #:
09569715
Filing Dt:
05/11/2000
Title:
METHOD OF RESPONDING TO I/O REQUEST AND ASSOCIATED REPLY DESCRIPTOR
100
Patent #:
Issue Dt:
08/31/2004
Application #:
09571399
Filing Dt:
05/15/2000
Title:
METHOD FOR INDEPENDENT DYNAMIC RANGE CONTROL
Assignor
1
Exec Dt:
08/14/2014
Assignee
1
1 YISHUN AVENUE 7
SINGAPORE, SINGAPORE 768923
Correspondence name and address
LATHAM & WATKINS LLP
650 TOWN CENTER DRIVE, SUITE 2000
COSTA MESA, CA 92626

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